公开(公告)号：US20220247077A1

公开(公告)日：2022-08-04

申请号：US17235415

申请日：2021-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Venumadhav BHAGAVATULA ,  Siu-Chuang Ivan LU ,  Sang Won SON

IPC: H01Q5/307 ,  H01Q5/42 ,  H01Q5/50 ,  H04B1/44

Abstract: A radio frequency integrated circuit (RFIC) and method of communication are provided. The RFIC includes phased-locked loop (PLL) and data stream circuitry and a plurality of tiles in communication with the PLL and data stream circuitry. The plurality of tiles includes comprising at least one tile for each frequency band of the RFIC. The plurality of tiles are configured to communicate a data stream signal between tiles in a cascading sequence. Each tile of the plurality of tiles includes a plurality of up/down conversion mixers for converting the data stream signal between an intermediate frequency (IF) and a radio frequency (RF). Each tile also includes a plurality of front end (FE) elements, each in communication with a corresponding antenna and an up/down conversion mixer of the plurality of up/down conversion mixers.

公开(公告)号：US20170222607A1

公开(公告)日：2017-08-03

申请号：US15137349

申请日：2016-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siddharth SETH ,  Venumadhav BHAGAVATULA ,  Ivan LU ,  Sang Won SON

IPC: H03F3/24 ,  H04W72/12 ,  H04B1/04 ,  H03F3/19 ,  H04L5/22

CPC classification number: H03F3/245 ,  H03F3/19 ,  H03F3/217 ,  H03F3/24 ,  H03F2200/451 ,  H04B1/0475 ,  H04B2001/0408 ,  H04L5/22 ,  H04W72/1263

Abstract: Apparatuses, systems, and methods for a digital power amplifier (DPA) to generate a monotonic and linear ramp-up and ramp-down for a time division multiple access (TDMA) slot transmission are described. In one aspect, a monotonic and linear amplitude-to-control input code relationship model is generated for the DPA and stored. When the DPA needs to generate a ramp-up or ramp-down, the stored monotonic and linear amplitude-to-control input code relationship model is used to shape the input control code before it is input into the DPA. A new monotonic and linear amplitude-to-control input code relationship model may be generated and stored if the operating conditions change. The apparatuses, systems, and methods described herein may be applied to a multi-standard broadband modem chip capable of 2G transmission.

公开(公告)号：US20170077904A1

公开(公告)日：2017-03-16

申请号：US15065433

申请日：2016-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Venumadhav BHAGAVATULA ,  Sriramkumar VENUGOPALAN ,  Siddharth SETH ,  Siuchuang Ivan LU ,  Sang Won SON

IPC: H03H11/28 ,  H03D7/12 ,  H03K17/693 ,  H03H11/32 ,  H03K17/691

CPC classification number: H03D7/125 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03H11/28 ,  H03H11/32 ,  H03K17/691 ,  H03K17/693

Abstract: An apparatus and method are provided. The apparatus includes a multiplexer, including a first input, a second input, a third input, and an output; a first transistor, including a gate, a first terminal, and a second terminal; a first variable capacitor, including a first terminal, a second terminal, and an input; a first inductor, including a first terminal and a second terminal; a second transistor, including a gate, a first terminal, and a second terminal; a second inductor mutually coupled to the first inductor, including a first terminal and a second terminal; a balun-bias switch, including a first input, a second input, a third input, and an output; a second capacitor, including a first terminal, and a second terminal; and a port-switch, including a first input, a second input, a third input, and an output.

Abstract translation: 提供了一种装置和方法。 该装置包括多路复用器，包括第一输入，第二输入，第三输入和输出; 第一晶体管，包括栅极，第一端子和第二端子; 第一可变电容器，包括第一端子，第二端子和输入端; 第一电感器，包括第一端子和第二端子; 第二晶体管，包括栅极，第一端子和第二端子; 第二电感器，其相互耦合到所述第一电感器，包括第一端子和第二端子; 平衡偏压开关，包括第一输入，第二输入，第三输入和输出; 包括第一端子和第二端子的第二电容器; 以及端口开关，包括第一输入端，第二输入端，第三输入端和输出端。

公开(公告)号：US20180041168A1

公开(公告)日：2018-02-08

申请号：US15277534

申请日：2016-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Venumadhav BHAGAVATULA ,  Siuchuang Ivan Lu ,  Sang Won Son

IPC: H03D7/14 ,  G06F17/50

CPC classification number: H03D7/1466 ,  H03D7/1441 ,  H03D7/1483 ,  H03D2200/0086

Abstract: An apparatus and a method. The apparatus includes passive mixers, wherein each of the passive mixers includes a first input for receiving BBI, a second input for receiving BBI, a third input for receiving BBQ, a fourth input for receiving BBQ, a fifth input for receiving a first clock signal with a unique phase shift within one of the passive mixers, a sixth input for receiving a second clock signal with a unique phase shift within one of the passive mixers, a seventh input for receiving a third clock signal with a unique phase shift within one of the passive mixers, an eighth input for receiving a fourth clock signal with a unique phase shift within one of the passive mixers, and at least one output; and a voltage-domain vector summation array connected to the output of each of the passive mixers.

公开(公告)号：US20170264242A1

公开(公告)日：2017-09-14

申请号：US15608254

申请日：2017-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Venumadhav BHAGAVATULA ,  Sriramkumar VENUGOPALAN ,  Siddharth SETH ,  Siuchuang Ivan LU ,  Sang Won SON

IPC: H03D7/12 ,  H03K17/693 ,  H03H11/32 ,  H03K17/691 ,  H03D7/14 ,  H03H11/28

CPC classification number: H03D7/125 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03H11/28 ,  H03H11/32 ,  H03K17/691 ,  H03K17/693

Abstract: An apparatus and method are provided. The apparatus includes a multiplexer, including first, second, and third inputs, and an output; a first transistor, including a gate connected to the first multiplexer, and first and second terminals; a first variable capacitor, including a first terminal connected to the first transistor, a second terminal, and an input; a first inductor, including a first terminal connected to the first transistor, and a second terminal connected to the second terminal of the first variable capacitor; a second transistor, including a gate connected to the output of the first multiplexer, a first terminal, and a second terminal connected to the second terminal of the first inductor; a second inductor mutually coupled to the first inductor, including a first and second terminals; and a balun-bias switch, including first, second, and third inputs, and an output connected to the second terminal of the second inductor.