公开(公告)号：US12293081B2

公开(公告)日：2025-05-06

申请号：US18310741

申请日：2023-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raghu Vamsi Krishna Talanki ,  Archita Khare ,  Eldho P. Mathew ,  Jin In So ,  Jong-Geon Lee ,  Venkata Ravi Shankar Jonnalagadda ,  Vishnu Charan Thummala

IPC: G06F3/06

Abstract: The present disclosure relates to field of Dual In-Line Memory Modules that discloses method and system for generating memory maps. The method comprises detecting, by computing system, at least one of DIMM and one or more Dynamic Random Access Memory (DRAM) chips associated with computing system. The one or more accelerators are configured in at least one of DIMM and one or more DRAM chips. Further, the method includes determining accelerator information for each of one or more accelerators via at least one of Serial Presence Detect (SPD) and Multi-Purpose Register (MPR) associated with at least one of DIMM and one or more DRAM chips. Method includes generating unique memory map for each of one or more accelerators based on accelerator information of corresponding one or more accelerators. As a result, performance of computing system may be improved as accelerator capabilities of one or more accelerators are effectively utilized.

公开(公告)号：US11797440B2

公开(公告)日：2023-10-24

申请号：US17854772

申请日：2022-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Raghu Vamsi Krishna Talanki ,  Eldho Pathiyakkara Thombra Mathew ,  Vishnu Charan Thummala ,  Vinod Kumar Srinivasan ,  Jin In So ,  Jong-Geon Lee

IPC: G06F12/06

CPC classification number: G06F12/063 ,  G06F2212/206

Abstract: A Near Memory Processing (NMP) dual in-line memory module (DIMM) for managing an address map is provided. The NMP DIMM includes: a static random-access memory (SRAM) provided on a Double Data Rate (DDR) interface; and an address management controller coupled to the SRAM, and configured to control the NMP DIMM to: receive a first indication from a host system to perform interface training for operating an SRAM space; perform the interface training using a first address map based on the first indication; receive a second indication from the host system indicating completion of the interface training for operating the SRAM space; switch from the first address map to a second address map for operating the SRAM space in response based on the second indication; and operate the SRAM space using the second address map.

公开(公告)号：US11195568B1

公开(公告)日：2021-12-07

申请号：US17060913

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Atishay ,  Anirudh B K ,  Rajeev Verma ,  Vishnu Charan Thummala

IPC: G11C11/406 ,  G11C29/42 ,  G11C11/4072

Abstract: Methods and systems for controlling refresh operations of a memory device. A method disclosed herein includes receiving, by a refresh controller of the memory device, a refresh command from a host for performing the refresh operation on a plurality of memory rows. The method further includes selecting, by the refresh controller, at least one memory row from the plurality of memory rows for the refresh operation using a refresh-row selection circuitry. The at least one memory row is selected by performing digital reading or analog reading of at least one row condition cell (RCC) and at least one supplemental cell that are connected to each memory row of the memory rows. The method further includes performing, by the refresh controller, the refresh operation on the selected at least one memory row.

公开(公告)号：US20230004489A1

公开(公告)日：2023-01-05

申请号：US17854772

申请日：2022-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Raghu Vamsi Krishna TALANKI ,  Eldho Pathiyakkara Thombra Mathew ,  Vishnu Charan Thummala ,  Vinod Kumar Srinivasan ,  Jin ln So ,  Jong-Geon Lee

IPC: G06F12/06

Abstract: A Near Memory Processing (NMP) dual in-line memory module (DIMM) for managing an address map is provided. The NMP DIMM includes: a static random-access memory (SRAM) provided on a Double Data Rate (DDR) interface; and an address management controller coupled to the SRAM, and configured to control the NMP DIMM to: receive a first indication from a host system to perform interface training for operating an SRAM space; perform the interface training using a first address map based on the first indication; receive a second indication from the host system indicating completion of the interface training for operating the SRAM space; switch from the first address map to a second address map for operating the SRAM space in response based on the second indication; and operate the SRAM space using the second address map.

公开(公告)号：US11922068B2

公开(公告)日：2024-03-05

申请号：US17666212

申请日：2022-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eldho Mathew Pathiyakkara Thombra ,  Ravi Shankar Venkata Jonnalagadda ,  Prashant Vishwanath Mahendrakar ,  Jinin So ,  Jong-Geon Lee ,  Vishnu Charan Thummala

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

Abstract: A Near Memory Processing (NMP) Dual In-line Memory Module (DIMM) is provided that includes random access memory (RAM), a Near-Memory-Processing (NMP) circuit and a first control port. The NMP circuit is for receiving a command from a host system, determining an operation to be performed on the RAM in response to the command, and a location of data within the RAM with respect to the determined operation. The first control port interacts with a second control port of the host system to enable the NMP circuit to exchange control information with the host system in response to the received command.