公开(公告)号：US20170331493A1

公开(公告)日：2017-11-16

申请号：US15488789

申请日：2017-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Seung YU ,  Sukyong KANG ,  Wonjoo YUN ,  Hyunui LEE ,  Jae-Hun JUNG

IPC: H03M13/09 ,  G06F11/10 ,  G11C29/52 ,  H03M13/00

CPC classification number: H03M13/098 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/52 ,  H03M13/611

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

公开(公告)号：US20190165808A1

公开(公告)日：2019-05-30

申请号：US16262127

申请日：2019-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Seung YU ,  Sukyong KANG ,  Wonjoo YUN ,  Hyunui LEE ,  Jae-Hun JUNG

IPC: H03M13/09 ,  H03M13/00 ,  G11C29/52 ,  G06F11/10

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.