公开(公告)号：US20170331493A1

公开(公告)日：2017-11-16

申请号：US15488789

申请日：2017-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Seung YU ,  Sukyong KANG ,  Wonjoo YUN ,  Hyunui LEE ,  Jae-Hun JUNG

IPC: H03M13/09 ,  G06F11/10 ,  G11C29/52 ,  H03M13/00

CPC classification number: H03M13/098 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/52 ,  H03M13/611

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

公开(公告)号：US20190165808A1

公开(公告)日：2019-05-30

申请号：US16262127

申请日：2019-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Seung YU ,  Sukyong KANG ,  Wonjoo YUN ,  Hyunui LEE ,  Jae-Hun JUNG

IPC: H03M13/09 ,  H03M13/00 ,  G11C29/52 ,  G06F11/10

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

公开(公告)号：US20170345754A1

公开(公告)日：2017-11-30

申请号：US15396633

申请日：2016-12-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Joo YUN ,  Suk-Yong KANG ,  Sang-Hoon SHIN ,  Hye-Seung YU ,  Hyun-Ui LEE ,  Jae-Hun JUNG

IPC: H01L23/522 ,  H01L23/525 ,  H01L25/065 ,  H02J50/12 ,  H01L23/528 ,  H01L23/48

CPC classification number: H01L23/5227 ,  H01F27/2804 ,  H01F38/14 ,  H01F2027/2809 ,  H01F2038/143 ,  H01L23/481 ,  H01L23/5256 ,  H01L23/528 ,  H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06541 ,  H02J50/12 ,  H04B5/0037 ,  H04B5/0075 ,  H05K1/0306 ,  H05K1/165 ,  H05K3/4629 ,  H05K2201/09709 ,  H05K2201/09845 ,  H05K2201/10098 ,  H05K2201/10159 ,  H05K2201/10181

Abstract: A three-dimensional (3D) inductor structure comprising: a first semiconductor die including: a first conductive pattern; and a second conductive pattern spaced apart from the first conductive pattern; a second semiconductor die stacked on the first semiconductor die, the second semiconductor die including: a third conductive pattern; a fourth conductive pattern spaced apart from the third conductive pattern; a first through-substrate via (TSV) penetrating the second semiconductor die and electrically connecting the first conductive pattern with the third conductive pattern; and a second TSV penetrating the second semiconductor die and electrically connecting the second conductive pattern with the fourth conductive pattern, and a first conductive connection pattern included in the first semiconductor die and electrically connecting a first end of the first conductive pattern with a first end of the second conductive pattern, or included in the second semiconductor die and electrically connecting a first end of the third conductive pattern with a first end of the fourth conductive pattern.