公开(公告)号：US11824023B2

公开(公告)日：2023-11-21

申请号：US17465964

申请日：2021-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonkyun Kwon ,  Chulyong Jang

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L24/05 ,  H01L21/76871 ,  H01L23/481 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05025

Abstract: A semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface. An active layer is disposed in a portion of the semiconductor substrate adjacent to the first surface. A through electrode extends in the semiconductor substrate in a vertical direction. The through electrode has a lower surface connected to the active layer and an upper surface positioned at a level lower than a level of the second surface of the semiconductor substrate. A passivation layer is disposed on the second surface of the semiconductor substrate. A bonding pad is arranged on a portion of the passivation layer and the upper surface of the through electrode. The bonding pad has a cross-section with a “T” shape in the vertical direction. The bonding pad is connected to the through electrode.

公开(公告)号：US12224258B2

公开(公告)日：2025-02-11

申请号：US18380404

申请日：2023-10-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonkyun Kwon ,  Chulyong Jang

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface. An active layer is disposed in a portion of the semiconductor substrate adjacent to the first surface. A through electrode extends in the semiconductor substrate in a vertical direction. The through electrode has a lower surface connected to the active layer and an upper surface positioned at a level lower than a level of the second surface of the semiconductor substrate. A passivation layer is disposed on the second surface of the semiconductor substrate. A bonding pad is arranged on a portion of the passivation layer and the upper surface of the through electrode. The bonding pad has a cross-section with a “T” shape in the vertical direction. The bonding pad is connected to the through electrode.

公开(公告)号：US20230075665A1

公开(公告)日：2023-03-09

申请号：US17875983

申请日：2022-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkyun Kwon ,  Jungseok Ahn ,  Kuyoung Kim

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor package includes a substrate, a plurality of semiconductor devices stacked on the substrate, an under-fill fillet on side surfaces of the plurality of semiconductor devices, and a molding resin surrounding the plurality of semiconductor devices. An uppermost end of the under-fill fillet includes a planar surface coplanar with an upper surface of a periphery of an uppermost semiconductor device among the plurality of semiconductor devices, and the molding resin completely covers the planar surface.