公开(公告)号：US20240347646A1

公开(公告)日：2024-10-17

申请号：US18755671

申请日：2024-06-27

申请人： ROHM CO., LTD.

发明人： Masaya UENO ,  Sawa HARUYAMA ,  Masaya SAITO

IPC分类号： H01L29/872 ,  H01L23/00 ,  H01L29/06 ,  H01L29/16 ,  H01L29/47

CPC分类号： H01L29/872 ,  H01L24/05 ,  H01L29/0692 ,  H01L29/47 ,  H01L29/0619 ,  H01L29/1608 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05647 ,  H01L2924/0132 ,  H01L2924/0133

摘要： A semiconductor device includes: a semiconductor layer including a semiconductor substrate and an epitaxial layer of a first conductivity type formed on the semiconductor substrate; a surface electrode containing at least one selected from the group consisting of an aluminum alloy and aluminum and formed on the semiconductor layer; and an impurity region of a second conductivity type formed on a surface layer portion of the epitaxial layer and forming a pn junction with the epitaxial layer, wherein the surface electrode includes a Schottky portion that is in contact with a surface of the semiconductor layer and forms a Schottky junction with the epitaxial layer.

公开(公告)号：US20230378018A1

公开(公告)日：2023-11-23

申请号：US18317632

申请日：2023-05-15

申请人： ROHM CO., LTD.

发明人： Hajime OKUDA ,  Yuto NISHIYAMA ,  Toru TAKUMA ,  Katsuaki YAMADA

IPC分类号： H01L23/367 ,  H01L23/00

CPC分类号： H01L23/367 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/06 ,  H01L24/32 ,  H01L24/29 ,  H01L24/45 ,  H01L24/73 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05655 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2924/01014 ,  H01L2224/06181 ,  H01L2224/05552 ,  H01L2224/29144 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45139 ,  H01L2224/45655 ,  H01L2224/45664 ,  H01L2224/45644 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48245 ,  H01L2224/48451 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/48101 ,  H01L2224/4901 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/73215 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/4945 ,  H01L23/49513

摘要： A semiconductor device includes: a substrate; a device region provided in the substrate; a terminal covering the device region in a plan view; a plurality of pseudo-bumps densely arranged on the terminal in a state of being opened from a wire; and at least one genuine bump arranged more sparsely than the plurality of the pseudo-bumps on the terminal in a state of being connected to the wire.

公开(公告)号：US11658139B2

公开(公告)日：2023-05-23

申请号：US17206337

申请日：2021-03-19

申请人： Samsung Electronics Co., Ltd.

发明人： Jaehyung Park ,  Seokho Kim ,  Hoonjoo Na ,  Seongmin Son ,  Kyuha Lee ,  Yikoan Hong

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L24/06 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05176 ,  H01L2224/05554 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05649 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06177 ,  H01L2224/06505 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/32145

摘要： A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures.

公开(公告)号：US20230154885A1

公开(公告)日：2023-05-18

申请号：US18049428

申请日：2022-10-25

申请人： Samsung Electronics Co., Ltd.

发明人： Jinyoung Kim ,  Jiyeong Kim ,  Okseon Yoon

IPC分类号： H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L23/29

CPC分类号： H01L24/73 ,  H01L21/563 ,  H01L23/295 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L25/18 ,  H01L25/50 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0567 ,  H01L2224/0568 ,  H01L2224/1317 ,  H01L2224/1318 ,  H01L2224/2929 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05617 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05663 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13117 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13138 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13163 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13181 ,  H01L2224/13183 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2224/16146 ,  H01L2224/29386 ,  H01L2224/32145 ,  H01L2224/73204

摘要： A semiconductor package includes a first semiconductor chip on a lower structure. A first underfill is between the first semiconductor chip and the lower structure. The first underfill includes a first portion adjacent to a center region of the first semiconductor chip, and a second portion adjacent to an edge region of the first semiconductor chip. The second portion has a higher degree of cure than the first portion. A plurality of inner connection terminals is between the first semiconductor chip and the lower structure. The plurality of inner connection terminals extends in the first underfill.

公开(公告)号：US10079230B2

公开(公告)日：2018-09-18

申请号：US15240009

申请日：2016-08-18

申请人： QUALCOMM Incorporated

发明人： Michael A. Stuber ,  Stuart B. Molin

IPC分类号： H01L29/66 ,  H01L27/082 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/73 ,  H01L29/732 ,  H01L29/739 ,  H01L29/744 ,  H01L27/088 ,  H01L29/06 ,  H01L21/683 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L23/00

CPC分类号： H01L27/0823 ,  H01L21/6835 ,  H01L21/823487 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/7317 ,  H01L29/732 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/781 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/1148 ,  H01L2224/1302 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/48 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/00

摘要： A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped to a conductivity type opposite that of the background, is formed at the second surface of the semiconductor layer. A second doped region of the same conductivity type as the background is formed at the second surface of the semiconductor layer, inside the first doped region. A portion of the semiconductor layer is removed at the first surface, exposing a new third surface. A third doped region is formed inside the semiconductor layer at the third surface. Electrical contact is made at least to the second doped region (via the second surface) and the third doped region (via the new third surface). In this way, vertical DMOS, IGBT, bipolar transistors, thyristors, and other types of devices can be fabricated in thinned semiconductor, or SOI layers.

公开(公告)号：US20180019218A1

公开(公告)日：2018-01-18

申请号：US15716534

申请日：2017-09-27

申请人： Infineon Technologies AG

发明人： Jens Peter Konrath ,  Jochen Hilsenbeck

IPC分类号： H01L23/00

CPC分类号： H01L24/03 ,  B81C1/00 ,  H01L24/05 ,  H01L24/06 ,  H01L29/40 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0381 ,  H01L2224/0383 ,  H01L2224/0391 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/05601 ,  H01L2224/05613 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05663 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/06181 ,  H01L2924/01029 ,  H01L2924/01014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01076 ,  H01L2924/0108

摘要： According to various embodiments an electronic component includes: at least one electrically conductive contact region; a contact pad including a self-segregating composition disposed over the at least one electrically conductive contact region; a segregation suppression structure disposed between the contact pad and the at least one electrically conductive contact region, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.

公开(公告)号：US09741693B2

公开(公告)日：2017-08-22

申请号：US14939253

申请日：2015-11-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chin-Fu Kao ,  Tsei-Chung Fu ,  Jing-Cheng Lin

IPC分类号： H01L25/065 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/04 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05638 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/08145 ,  H01L2224/1161 ,  H01L2224/11616 ,  H01L2224/11831 ,  H01L2224/13009 ,  H01L2224/13019 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/1601 ,  H01L2224/16012 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73201 ,  H01L2224/73204 ,  H01L2224/80075 ,  H01L2224/80203 ,  H01L2224/80896 ,  H01L2224/8101 ,  H01L2224/81011 ,  H01L2224/81012 ,  H01L2224/81022 ,  H01L2224/81075 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/83075 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/1434 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/01014 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/07025 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2924/00012 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2924/01029 ,  H01L2924/00

摘要： The present disclosure provides a semiconductor package, including a first device having a first joining surface, a first conductive component at least partially protruding from the first joining surface, a second device having a second joining surface facing the first joining surface, and a second conductive component at least exposing from the second joining surface. The first conductive component and the second conductive component form a joint having a first beak. The first beak points to either the first joining surface or the second joining surface.

公开(公告)号：US20160005697A1

公开(公告)日：2016-01-07

申请号：US14621574

申请日：2015-02-13

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hyun-Pil Noh ,  Jeong-Woon Kim ,  Seok-Ha Lee

IPC分类号： H01L23/00

CPC分类号： H01L23/562 ,  H01L23/3114 ,  H01L23/5283 ,  H01L23/585 ,  H01L24/02 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02235 ,  H01L2224/0239 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05601 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/45424 ,  H01L2224/45444 ,  H01L2224/45447 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01048 ,  H01L2924/01013 ,  H01L2924/01029

摘要： Provided are a semiconductor chip, a semiconductor package and a fabricating method thereof, which can reduce or prevent cracks from being generated or propagated due to an external pressure. The semiconductor chip includes a semiconductor substrate including a first region and a second region, a plurality of interlayer insulation layers formed on the semiconductor substrate, a first crack stopper formed in the plurality of interlayer insulation layers of the first region, an interconnector formed in the plurality of interlayer insulation layers of the second region, a pad wire formed on the plurality of interlayer insulation layers, electrically connected to the interconnector in the second region and extending to the first region, a bonding pad on the plurality of interlayer insulation layers of the first region, electrically connected to the pad wire, and a protection layer covering the pad wire and exposing the bonding pad. The first crack stopper is positioned at a lower level than the bonding pad and is formed to completely surround the bonding pad while not overlapping with the bonding pad and not being connected to the pad wire.

摘要翻译： 提供了可以减少或防止由于外部压力而产生或传播裂纹的半导体芯片，半导体封装及其制造方法。 半导体芯片包括：半导体衬底，包括第一区域和第二区域;形成在半导体衬底上的多个层间绝缘层，形成在第一区域的多个层间绝缘层中的第一裂纹阻挡层，形成在第一区域中的互连器 所述第二区域的多个层间绝缘层，形成在所述多个层间绝缘层上的焊盘线，与所述第二区域中的所述互连器电连接并延伸到所述第一区域，所述焊盘在所述多个层间绝缘层上， 第一区域，电连接到焊盘焊丝，以及覆盖焊盘焊丝并暴露焊盘的保护层。 第一裂纹阻挡件位于比接合焊盘更低的高度，并且形成为完全围绕接合焊盘而不与接合焊盘重叠而不与焊盘连接。

公开(公告)号：US09129955B2

公开(公告)日：2015-09-08

申请号：US12503553

申请日：2009-07-15

申请人： Abram M. Castro ,  Mark A. Gerber

发明人： Abram M. Castro ,  Mark A. Gerber

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L24/13 ,  H01L23/49811 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/0558 ,  H01L2224/05638 ,  H01L2224/05655 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099

摘要： A semiconductor chip (102) assembled on a substrate (101). The substrate has a first surface (101a) including conductive traces (110), which have a first length (111) and a first width (112), the first width being uniform along the first length, and further a pitch (114) to respective adjacent traces. The semiconductor chip has a second surface (102a) including contact pads (121); the second surface faces the first surface spaced apart by a gap (130). A conductive pillar (140) contacts each contact pad; the pillar includes a metal core (141) and a solder body (142), which connects the core to the respective trace across the gap. The pillar core (141) has an oblong cross section of a second width (151) and a second length (152) greater than the second width. Trace pitch (141) is equal to or smaller than twice the second width (151). The trace pitch is equal to or smaller than the second length (152).

摘要翻译： 组装在基板（101）上的半导体芯片（102）。 衬底具有包括具有第一长度（111）和第一宽度（112）的导电迹线（110）的第一表面（101a），第一宽度沿着第一长度是均匀的，并且还有一个间距（114）到 相应的相邻轨迹。 半导体芯片具有包括接触焊盘（121）的第二表面（102a）; 所述第二表面面向所述第一表面，间隔开间隙（130）。 导电柱（140）接触每个接触垫; 支柱包括金属芯（141）和焊料体（142），其将芯连接到穿过间隙的相应迹线。 柱芯（141）具有第二宽度（151）的长方形横截面和大于第二宽度的第二长度（152）。 痕迹间距（141）等于或小于第二宽度（151）的两倍。 迹线间距等于或小于第二长度（152）。

公开(公告)号：US09112001B2

公开(公告)日：2015-08-18

申请号：US14173406

申请日：2014-02-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Pao Shu ,  Chun-wen Cheng ,  Kuei-Sung Chang ,  Hsin-Ting Huang ,  Shang-Ying Tsai ,  Jung-Huei Peng

IPC分类号： H01L21/30 ,  H01L21/768 ,  B81C1/00 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L21/76838 ,  B81C1/00238 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/49838 ,  H01L23/528 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/0362 ,  H01L2224/04026 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05617 ,  H01L2224/05638 ,  H01L2224/061 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/26145 ,  H01L2224/29011 ,  H01L2224/29014 ,  H01L2224/29017 ,  H01L2224/2902 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29117 ,  H01L2224/29124 ,  H01L2224/29138 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29181 ,  H01L2224/301 ,  H01L2224/32058 ,  H01L2224/321 ,  H01L2224/32106 ,  H01L2224/32148 ,  H01L2224/83203 ,  H01L2224/83365 ,  H01L2224/83805 ,  H01L2225/06527 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/01014 ,  H01L2924/01037 ,  H01L2924/01032 ,  H01L2924/00 ,  H01L2924/0132 ,  H01L2924/00014

摘要： A method of forming a package system includes providing a first substrate having a metallic pad and at least one metallic guard ring. The method further includes bonding the metallic pad of the first substrate with a semiconductor pad of a second substrate, wherein the at least one metallic guard ring is configured to at least partially interact with the semiconductor pad to form at least a first portion of an electrical bonding material between the first and second substrates.

摘要翻译： 形成封装系统的方法包括提供具有金属焊盘和至少一个金属保护环的第一基板。 该方法还包括用第二衬底的半导体焊盘接合第一衬底的金属焊盘，其中至少一个金属保护环被配置为至少部分地与半导体焊盘相互作用以形成至少第一部分的电 在第一和第二基板之间接合材料。