公开(公告)号：US20180330948A1

公开(公告)日：2018-11-15

申请号：US15808993

申请日：2017-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hyun KWON ,  Daehyun JANG

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/31144 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/40117

Abstract: A method of fabricating a three-dimensional semiconductor device comprises stacking first hardmask layers and second hardmask layers on a lower layer including a pattern region and a buffer region adjacent to the pattern region, the second hardmask layers and the first hardmask layers for forming a first hardmask pattern and a second hardmask pattern, patterning the second hardmask layer to form the second hardmask pattern including a plurality of first mask holes on the pattern region and at least one recess on the buffer region, the plurality of first mask holes exposing the first hardmask layer, and etching the first hardmask layer using the second hardmask pattern as an etch mask to form the first hardmask pattern including a plurality of etch mask holes on the pattern region and at least one buffer mask hole on the buffer region, the plurality of etch mask holes exposing a top surface of the lower layer, the at least one buffer mask hole having a bottom surface spaced apart from the top surface of the lower layer.