IMAGE SENSOR HAVING REDUCED PARASITIC CAPACITANCE

    公开(公告)号:US20210120200A1

    公开(公告)日:2021-04-22

    申请号:US16890422

    申请日:2020-06-02

    Abstract: An image sensor, including a pixel array including a plurality of pixels connected to row lines extending in a first direction and column lines extending in a second direction intersecting the first direction; a ramp voltage generator configured to output a ramp voltage; a sampling circuit including a plurality of comparators, each comparator of the plurality of comparators having a first input terminal connected to a column of the column lines and a second input terminal configured to receive the ramp voltage; and an analog-to-digital converter configured to convert an output of the plurality of comparators to a digital signal, wherein the plurality of comparators include a first comparator connected to a first column line, and a second comparator connected to a second column line adjacent to the first column line in the first direction, wherein each of the first comparator and the second comparator includes a first transistor and a second transistor disposed sequentially in the second direction, and wherein a gap between the first transistor of the first comparator and the second transistor of the first comparator is different from a gap between the first transistor of the second comparator and the second transistor of the second comparator.

    Image sensor having reduced parasitic capacitance

    公开(公告)号:US11606523B2

    公开(公告)日:2023-03-14

    申请号:US16890422

    申请日:2020-06-02

    Abstract: An image sensor, including a pixel array including a plurality of pixels connected to row lines extending in a first direction and column lines extending in a second direction intersecting the first direction; a ramp voltage generator configured to output a ramp voltage; a sampling circuit including a plurality of comparators, each comparator of the plurality of comparators having a first input terminal connected to a column of the column lines and a second input terminal configured to receive the ramp voltage; and an analog-to-digital converter configured to convert an output of the plurality of comparators to a digital signal, wherein the plurality of comparators include a first comparator connected to a first column line, and a second comparator connected to a second column line adjacent to the first column line in the first direction, wherein each of the first comparator and the second comparator includes a first transistor and a second transistor disposed sequentially in the second direction, and wherein a gap between the first transistor of the first comparator and the second transistor of the first comparator is different from a gap between the first transistor of the second comparator and the second transistor of the second comparator.

    Electronic circuit for configuring amplifying circuit configured to output voltage including low noise

    公开(公告)号:US11503239B2

    公开(公告)日:2022-11-15

    申请号:US16822930

    申请日:2020-03-18

    Abstract: An electronic circuit is provided. The electronic circuit includes a first current generating circuit configured to output a first operating current based on a first operating voltage; and an input circuit configured to: receive a first current corresponding to a first input voltage and a second current corresponding to a second input voltage, wherein the first current and the second current are based on the first operating current; receive a third current and a fourth current that are generated based on the first operating voltage; and generate a fifth current corresponding to the second input voltage based on a second operating current. The electronic circuit is configured to generate an output voltage that is associated with a difference between the first input voltage and the second input voltage based on the second current, the fourth current and the fifth current, and the fourth current corresponds to the third current.

Patent Agency Ranking