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公开(公告)号：US20200168271A1
公开(公告)日：2020-05-28
申请号：US16421855
申请日：2019-05-24
发明人： Ihor VASYLTSOV , Youngnam HWANG , Jinmin KIM , Yongha PARK , Hyunsik PARK , Jaewon YANG
IPC分类号： G11C11/54 , G11C11/4096 , G11C11/408 , G11C11/4091 , G06N3/04
摘要： A semiconductor memory device includes a memory cell array including first memory cells and second memory cell, and a peripheral circuit. When a first command, a first address, and first input data are received, the peripheral circuit reads first data from the first memory cells based on the first address in response to the first command, performs a first operation by using the first data and the first input data, and reads second data from the second memory cells by using a result of the first operation.
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公开(公告)号：US20230153589A1
公开(公告)日：2023-05-18
申请号：US17983058
申请日：2022-11-08
发明人： Youngnam HWANG
IPC分类号： G06N3/063
CPC分类号： G06N3/063
摘要： A neuromorphic device includes a plurality of cell tiles, each of the plurality of cell tiles including a cell array including a plurality of memory cells storing weights of a neural network, a row driver connected to the plurality of memory cells through a plurality of row lines, and cell analog-digital converters (ADCs) connected to the plurality of memory cells through a plurality of column lines, and a controller configured to select, form the plurality of cell tiles, a plurality of valid cell tiles storing the weights, execute a neural network-based arithmetic operation based on the plurality of valid cell tiles, and redundantly store weights of a first layer among a plurality of layers included in the neural network in a plurality of first valid cell tiles that are divided into a plurality of first tile groups.
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公开(公告)号：US20230005529A1
公开(公告)日：2023-01-05
申请号：US17747491
申请日：2022-05-18
发明人： Youngnam HWANG
摘要： A neuromorphic device includes a plurality of cell tiles including a cell array including a plurality of memory cells storing a weight of a neural network, a row driver connected to the plurality of memory cells, and cell analog-digital converters connected to the plurality of memory cells and converting cell currents into a plurality of pieces of digital cell data, a reference tile including a plurality of reference cells, a reference row driver connected to the plurality of reference cells, and reference analog-digital converters connected to the plurality of reference cells and converting reference currents read via the plurality of reference column lines into a plurality of pieces of digital reference data, and a comparator circuit configured to compare the plurality of pieces of digital cell data with the plurality of pieces of digital reference data, respectively.
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公开(公告)号：US20230386601A1
公开(公告)日：2023-11-30
申请号：US18204020
申请日：2023-05-31
发明人： Youngnam HWANG
CPC分类号： G11C29/808 , G11C29/802 , G11C29/52
摘要： A neuromorphic device includes a memory cell array including first resistive memory cells connected to word lines, bit lines and source lines, second resistive memory cells connected to the word lines, at least one redundancy bit line and at least one redundancy source line, third resistive memory cells connected to at least one redundancy word line, the bit lines and the source lines. The memory cell array stores data corresponding to a weight of a neural network in the first resistive memory cells, and is configured to generate a plurality of read currents based on input signals and the data. The neuromorphic device further includes an analog to digital converter (ADC) circuit configured to convert the plurality of read currents into a plurality of digital signals.
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公开(公告)号：US20230038384A1
公开(公告)日：2023-02-09
申请号：US17717339
申请日：2022-04-11
发明人： Youngnam HWANG
摘要： A neuromorphic computing device a method of controlling thereof are provided. The neuromorphic computing device includes a first memory cell array including resistive memory cells that are connected to wordlines, bitlines and source lines, and configured to store data and generate read currents based on input signals and the data; a second memory cell array including reference resistive memory cells that are connected to reference wordlines, reference bitlines and reference source lines, and configured to generate reference currents; and an analog-to-digital converting circuit configured to convert the read currents into digital signals based on the reference currents, wherein a voltage is applied to the reference wordlines, the reference resistive memory cells are arranged in columns to form reference columns, and the reference columns are configured to generate column currents, and one of the reference currents is generated by averaging at least two of the column currents.
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公开(公告)号：US20210334633A1
公开(公告)日：2021-10-28
申请号：US17129280
申请日：2020-12-21
发明人： Youngnam HWANG
摘要： A neuromorphic computing device includes a first memory cell array comprising a plurality of resistive memory cells and configured to output a plurality of read currents through a plurality of bit lines or source lines; a second memory cell array comprising a plurality of reference resistive memory cells and configured to output at least one reference current through at least one reference bit line or at least one reference source line; a current-to-voltage converting circuit configured to output a plurality of signal voltages respectively corresponding to the plurality of read currents and output at least one reference voltage corresponding to the at least one reference current; and an analog-to-digital converting circuit configured to convert the plurality of signal voltages to a plurality of digital signals using the at least one reference voltage and output the plurality of digital signals.
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公开(公告)号：US20210250028A1
公开(公告)日：2021-08-12
申请号：US17242737
申请日：2021-04-28
发明人： Hyungdal KWON , Seungwook LEE , Youngnam HWANG
IPC分类号： H03K19/1776 , G06F30/327
摘要： An electronic system and an operation method thereof are disclosed. A method of an electronic system including a field programmable gate array (FPGA) includes: synthesizing, by processing circuitry, code of a high level language into code of a hardware description language; designing, by the processing circuitry, a circuit of an intellectual property (IP) block included in the field programmable gate array according to the code of the hardware description language; and generating, by the processing circuitry, a database containing reference assembly code corresponding to the code of the high level language and information about a circuit configuration of the intellectual property block.
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公开(公告)号：US20140113429A1
公开(公告)日：2014-04-24
申请号：US14143760
申请日：2013-12-30
发明人： Myung Jin KANG , Youngnam HWANG
IPC分类号： H01L45/00
CPC分类号： H01L45/1683 , H01L27/2409 , H01L45/06
摘要： According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane.
摘要翻译： 根据示例实施例，可变电阻存储器件在衬底上包括欧姆图案; 第一电极图案，包括具有板形并接触欧姆图案的顶表面的第一部分和从第一部分的一端延伸到顶部的第二部分; 电连接到第一电极图案的可变电阻图案; 以及电连接到所述可变电阻图案的第二电极图案，其中所述欧姆图案的一端和所述第一部分的另一端设置在同一平面上。
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