公开(公告)号：US10712662B2

公开(公告)日：2020-07-14

申请号：US15405612

申请日：2017-01-13

申请人： Samsung Electronics Co., Ltd. ,  Dongjin Semichem Co., Ltd.

发明人： Jin-A Ryu ,  Jung-Youl Lee ,  Kyung-Lyul Moon ,  Yool Kang ,  Hyun-Jin Kim ,  Yu-Jin Jeoung ,  Man-Ho Han

IPC分类号： C08G18/02 ,  G03F7/11 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/027 ,  H01L49/02 ,  C09D175/00 ,  G03F7/004 ,  G03F7/09 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  G03F7/38 ,  H01L21/306 ,  H01L21/308

摘要： A method of forming a pattern is disclosed. The method includes preparing a composition that includes a solvent and a polymer including a repeating unit in which at least one isocyanurate unit having a first structure is connected to another isocyanurate unit having a second structure different from the first structure; applying the composition on a substrate to form an underlayer; forming a photoresist layer on the underlayer; etching the photoresist layer to form a photoresist pattern; and patterning the substrate using the photoresist pattern.

公开(公告)号：US09099470B2

公开(公告)日：2015-08-04

申请号：US14208456

申请日：2014-03-13

申请人： Samsung Electronics Co., Ltd.

发明人： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

IPC分类号： H01L21/033 ,  H01L23/528 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L27/115 ,  H01L21/768 ,  H01L27/108

CPC分类号： H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

摘要翻译： 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

公开(公告)号：US09093454B2

公开(公告)日：2015-07-28

申请号：US14186617

申请日：2014-02-21

申请人： Samsung Electronics Co., Ltd.

发明人： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/115

CPC分类号： H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

摘要翻译： 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。