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公开(公告)号：US20230326506A1
公开(公告)日：2023-10-12
申请号：US17718759
申请日：2022-04-12
Applicant: SanDisk Technologies LLC
Inventor： Michael Grobis , James W. Reiner , Michael Nicolas Albert Tran , Juan P. Saenz , Gerrit Jan Hemink
CPC classification number: G11C11/1659 , G11C7/20 , G11C13/003 , H01L25/0657 , H01L25/18 , H01L24/08 , H01L2224/08145 , H01L2924/1431 , H01L2924/1443
Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test. Techniques are also presented for initializing a cross-point array, for both first fire and cold start, by using voltage levels shifted from half-select voltage levels used in a standard memory access.
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公开(公告)号：US20230267981A1
公开(公告)日：2023-08-24
申请号：US17677666
申请日：2022-02-22
Applicant: SanDisk Technologies LLC
Inventor： Ward Parkinson , James O'Toole , Thomas Trent , Nathan Franklin , Michael Grobis , James W. Reiner , Hans Jurgen Richter , Michael Nicolas Albert Tran
CPC classification number: G11C11/1673 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/72
Abstract: Technology is disclosed for improving read margin in a cross-point memory array. Drive transistors pass a read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to the drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor which improves read margin. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector. Reducing Ihold of the threshold switching selector improves read margin.
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公开(公告)号：US12148459B2
公开(公告)日：2024-11-19
申请号：US17677666
申请日：2022-02-22
Applicant: SanDisk Technologies LLC
Inventor： Ward Parkinson , James O'Toole , Thomas Trent , Nathan Franklin , Michael Grobis , James W. Reiner , Hans Jurgen Richter , Michael Nicolas Albert Tran
Abstract: Technology for read in a cross-point memory array. Drive transistors pass read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to a drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector.
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公开(公告)号：US11894037B2
公开(公告)日：2024-02-06
申请号：US17718759
申请日：2022-04-12
Applicant: SanDisk Technologies LLC
Inventor： Michael Grobis , James W. Reiner , Michael Nicolas Albert Tran , Juan P. Saenz , Gerrit Jan Hemink
CPC classification number: G11C11/1659 , G11C7/20 , G11C13/003 , H01L24/08 , H01L25/0657 , H01L25/18 , H01L2224/08145 , H01L2924/1431 , H01L2924/1443
Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test. Techniques are also presented for initializing a cross-point array, for both first fire and cold start, by using voltage levels shifted from half-select voltage levels used in a standard memory access.
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