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公开(公告)号：US11688446B2
公开(公告)日：2023-06-27
申请号：US17846684
申请日：2022-06-22
Applicant: SanDisk Technologies LLC
Inventor： Michael Nicolas Albert Tran , Ward Parkinson , Michael Grobis , Nathan Franklin
CPC classification number: G11C11/1659 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/1695 , G11C11/1697 , H01L27/222 , H01L43/02 , H01L43/08 , H01L27/2481
Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.
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公开(公告)号：US20220108759A1
公开(公告)日：2022-04-07
申请号：US17061820
申请日：2020-10-02
Applicant: SanDisk Technologies LLC
Inventor： Michael Nicolas Albert Tran , Michael Grobis
Abstract: Non-volatile memory structures for performing compute-in-memory inferencing for neural networks are presented. A memory array is formed according to a crosspoint architecture with a memory cell at each crosspoint junction. The multi-levels memory cells (MLCs) are formed of multiple of ultra-thin dielectric layers separated by metallic layers, where programming of the memory cell is done by selectively breaking down one or more of the dielectric layers by selecting the write voltage level. In an alternate set of embodiments, the memory cells are formed as anti-fuses.
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公开(公告)号：US11972787B2
公开(公告)日：2024-04-30
申请号：US17824806
申请日：2022-05-25
Applicant: SanDisk Technologies LLC
Inventor： Michael Nicolas Albert Tran , Michael K. Grobis , Ward Parkinson , Nathan Franklin
CPC classification number: G11C11/1659 , G06F11/1044 , G11C11/161 , G11C11/1673 , G11C11/1675
Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.
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公开(公告)号：US20230101414A1
公开(公告)日：2023-03-30
申请号：US17552143
申请日：2021-12-15
Applicant: SanDisk Technologies LLC
Inventor： Martin Hassner , Michael Nicolas Albert Tran , Ward Parkinson , Michael Grobis , Nathan Franklin , Raj Ramanujan
Abstract: Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the first ECC mode (for a given raw bit error rate (RBER)). However, the RBER may be lower when using the second ECC mode. Therefore, the first and second ECC modes may result in about the same probability of an undetectable error (or mis-correction).
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公开(公告)号：US11081174B2
公开(公告)日：2021-08-03
申请号：US16912719
申请日：2020-06-26
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Zhaoqiang Bai , Mac D. Apodaca , Michael K. Grobis , Michael Nicolas Albert Tran , Neil Leslie Robertson , Gerardo A. Bertero
Abstract: A two-step SET pulse may be applied to a phase change material of a phase change memory cell in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.
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Patent Agency Ranking
公开(公告)号：US20240265958A1
公开(公告)日：2024-08-08
申请号：US18618754
申请日：2024-03-27
Applicant: SanDisk Technologies LLC
Inventor： Michael Nicolas Albert Tran , Michael K. Grobis , Ward Parkinson , Nathan Franklin
CPC classification number: G11C11/1659 , G06F11/1044 , G11C11/161 , G11C11/1673 , G11C11/1675
Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.
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公开(公告)号：US11972822B2
公开(公告)日：2024-04-30
申请号：US17552143
申请日：2021-12-15
Applicant: SanDisk Technologies LLC
Inventor： Martin Hassner , Michael Nicolas Albert Tran , Ward Parkinson , Michael Grobis , Nathan Franklin , Raj Ramanujan
CPC classification number: G11C29/42 , G11C29/1201 , G11C29/18 , G11C29/4401 , G11C2029/1802
Abstract: Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the first ECC mode (for a given raw bit error rate (RBER)). However, the RBER may be lower when using the second ECC mode. Therefore, the first and second ECC modes may result in about the same probability of an undetectable error (or mis-correction).
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公开(公告)号：US20230326506A1
公开(公告)日：2023-10-12
申请号：US17718759
申请日：2022-04-12
Applicant: SanDisk Technologies LLC
Inventor： Michael Grobis , James W. Reiner , Michael Nicolas Albert Tran , Juan P. Saenz , Gerrit Jan Hemink
CPC classification number: G11C11/1659 , G11C7/20 , G11C13/003 , H01L25/0657 , H01L25/18 , H01L24/08 , H01L2224/08145 , H01L2924/1431 , H01L2924/1443
Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test. Techniques are also presented for initializing a cross-point array, for both first fire and cold start, by using voltage levels shifted from half-select voltage levels used in a standard memory access.
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公开(公告)号：US20230267981A1
公开(公告)日：2023-08-24
申请号：US17677666
申请日：2022-02-22
Applicant: SanDisk Technologies LLC
Inventor： Ward Parkinson , James O'Toole , Thomas Trent , Nathan Franklin , Michael Grobis , James W. Reiner , Hans Jurgen Richter , Michael Nicolas Albert Tran
CPC classification number: G11C11/1673 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/72
Abstract: Technology is disclosed for improving read margin in a cross-point memory array. Drive transistors pass a read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to the drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor which improves read margin. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector. Reducing Ihold of the threshold switching selector improves read margin.
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公开(公告)号：US11682442B2
公开(公告)日：2023-06-20
申请号：US17846678
申请日：2022-06-22
Applicant: SanDisk Technologies LLC
Inventor： Michael Nicolas Albert Tran , Ward Parkinson , Michael Grobis , Nathan Franklin
CPC classification number: G11C11/1659 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/1695 , G11C11/1697 , H01L27/222 , H01L43/02 , H01L43/08 , H01L27/2481
Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.
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