公开(公告)号：US12205638B2

公开(公告)日：2025-01-21

申请号：US17939818

申请日：2022-09-07

Applicant: SanDisk Technologies LLC

Inventor： Nathan Franklin ,  Ward Parkinson ,  Michael Grobis ,  James O'Toole

IPC: G11C11/56 ,  G11C11/16 ,  H01L23/00 ,  H01L25/065 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

公开(公告)号：US20230259149A1

公开(公告)日：2023-08-17

申请号：US17672961

申请日：2022-02-16

Applicant: SanDisk Technologies LLC

Inventor： James O'Toole ,  Ward Parkinson ,  Thomas Trent

IPC: G05F3/26

CPC classification number: G05F3/26

Abstract: A circuit is provided that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output terminal of the circuit, the second terminal of the second transistor is coupled to the power supply bus, and the third terminal of the second transistor is coupled to the third terminal of the first transistor. The second transistor conducts a second current proportional to the first current substantially independent of distance between the first transistor and the second transistor.

公开(公告)号：US20220108740A1

公开(公告)日：2022-04-07

申请号：US17061636

申请日：2020-10-02

Applicant: SanDisk Technologies LLC

Inventor： Ward Parkinson ,  James O'Toole ,  Nathan Franklin ,  Thomas Trent

IPC: G11C11/16

Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may turned on while the pMOSFET is turned off. The nMOSFET provides a higher resistance in place of the decreased resistance of the pMOSFET to amplify a signal at a sense circuit to allow accurate sensing of the voltage across the memory cell.

公开(公告)号：US12148459B2

公开(公告)日：2024-11-19

申请号：US17677666

申请日：2022-02-22

Applicant: SanDisk Technologies LLC

Inventor： Ward Parkinson ,  James O'Toole ,  Thomas Trent ,  Nathan Franklin ,  Michael Grobis ,  James W. Reiner ,  Hans Jurgen Richter ,  Michael Nicolas Albert Tran

IPC: G11C11/16 ,  G11C13/00 ,  H10N50/10 ,  H10N70/20

Abstract: Technology for read in a cross-point memory array. Drive transistors pass read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to a drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector.

公开(公告)号：US11971736B2

公开(公告)日：2024-04-30

申请号：US17672961

申请日：2022-02-16

Applicant: SanDisk Technologies LLC

Inventor： James O'Toole ,  Ward Parkinson ,  Thomas Trent

IPC: G05F3/00 ,  G05F3/26

CPC classification number: G05F3/26

Abstract: A circuit is provided that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output terminal of the circuit, the second terminal of the second transistor is coupled to the power supply bus, and the third terminal of the second transistor is coupled to the third terminal of the first transistor. The second transistor conducts a second current proportional to the first current substantially independent of distance between the first transistor and the second transistor.

公开(公告)号：US20220157376A1

公开(公告)日：2022-05-19

申请号：US17099030

申请日：2020-11-16

Applicant: SanDisk Technologies LLC

Inventor： Nathan Franklin ,  Ward Parkinson ,  Michael Grobis ,  James O'Toole

IPC: G11C11/56 ,  H01L25/065 ,  H01L23/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16

Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

公开(公告)号：US20220293156A1

公开(公告)日：2022-09-15

申请号：US17828905

申请日：2022-05-31

Applicant: SanDisk Technologies LLC

Inventor： Ward Parkinson ,  James O'Toole ,  Nathan Franklin ,  Thomas Trent

IPC: G11C11/16

Abstract: A control circuit is configured to connect to a cross-point memory array in which each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET in a conductive state while the nMOSFET is in a non-conductive state. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be in a conductive state.

公开(公告)号：US11222678B1

公开(公告)日：2022-01-11

申请号：US17061836

申请日：2020-10-02

Applicant: SanDisk Technologies LLC

Inventor： Ward Parkinson ,  James O'Toole ,  Nathan Franklin ,  Thomas Trent

IPC: G11C11/16 ,  H01L27/22

Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM device, is connected in series with a threshold switching selector, such as an ovonic threshold switch. In a two-layer cross-point structure with such memory cells, the MRAM devices in one layer are inverted relative to the MRAM devices in the other layer. This can allow for the transient voltage spike placed across the MRAM device when the threshold switching selector first turns on in a sensing operation to dissipate more rapidly, reducing the risk of changing a stored data state before it can be sensed.

公开(公告)号：US11854592B2

公开(公告)日：2023-12-26

申请号：US17828905

申请日：2022-05-31

Applicant: SanDisk Technologies LLC

Inventor： Ward Parkinson ,  James O'Toole ,  Nathan Franklin ,  Thomas Trent

IPC: G11C11/16 ,  H10N50/80

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H10N50/80

Abstract: A control circuit is configured to connect to a cross-point memory array in which each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET in a conductive state while the nMOSFET is in a non-conductive state. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be in a conductive state.

公开(公告)号：US20230267981A1

公开(公告)日：2023-08-24

申请号：US17677666

申请日：2022-02-22

Applicant: SanDisk Technologies LLC

Inventor： Ward Parkinson ,  James O'Toole ,  Thomas Trent ,  Nathan Franklin ,  Michael Grobis ,  James W. Reiner ,  Hans Jurgen Richter ,  Michael Nicolas Albert Tran

IPC: G11C11/16 ,  G11C13/00

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/72

Abstract: Technology is disclosed for improving read margin in a cross-point memory array. Drive transistors pass a read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to the drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor which improves read margin. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector. Reducing Ihold of the threshold switching selector improves read margin.