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公开(公告)号：US12237010B2
公开(公告)日：2025-02-25
申请号：US17939826
申请日：2022-09-07
Applicant: SanDisk Technologies LLC
Inventor： Nathan Franklin , Ward Parkinson , Michael Grobis , James O'Toole
Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.
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公开(公告)号：US11978491B2
公开(公告)日：2024-05-07
申请号：US17485129
申请日：2021-09-24
Applicant: SanDisk Technologies LLC
Inventor： Michael Nicolas Albert Tran , Ward Parkinson , Michael Grobis , Nathan Franklin , Raj Ramanujan
IPC: G11C11/16 , G06F11/10 , H01L25/065 , H10B61/00
CPC classification number: G11C11/1673 , G06F11/1068 , G11C11/161 , G11C11/1659 , H10B61/10 , H01L25/0657 , H01L2225/06562
Abstract: Technology for reading reversible resistivity cells in a memory array when using a current-force read is disclosed. The memory cells are first read using a current-force referenced read. If the current-force referenced read is successful, then results of the current-force referenced read are returned. If the current-force referenced read is unsuccessful, then a current-force self-referenced read (SRR) is performed and results of the current-force SRR are returned. In an aspect this mixed current-force read is used for MRAM cells, which are especially challenging to read.
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公开(公告)号：US20230386543A1
公开(公告)日：2023-11-30
申请号：US17824806
申请日：2022-05-25
Applicant: SanDisk Technologies LLC
Inventor： Michael Nicolas Albert Tran , Michael K. Grobis , Ward Parkinson , Nathan Franklin
CPC classification number: G11C11/1659 , G11C11/161 , G11C11/1673 , G11C11/1675 , G06F11/1044
Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.
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公开(公告)号：US11488662B2
公开(公告)日：2022-11-01
申请号：US17099030
申请日：2020-11-16
Applicant: SanDisk Technologies LLC
Inventor： Nathan Franklin , Ward Parkinson , Michael Grobis , James O'Toole
Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.
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公开(公告)号：US11688446B2
公开(公告)日：2023-06-27
申请号：US17846684
申请日：2022-06-22
Applicant: SanDisk Technologies LLC
Inventor： Michael Nicolas Albert Tran , Ward Parkinson , Michael Grobis , Nathan Franklin
CPC classification number: G11C11/1659 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/1695 , G11C11/1697 , H01L27/222 , H01L43/02 , H01L43/08 , H01L27/2481
Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.
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Patent Agency Ranking
公开(公告)号：US20220293156A1
公开(公告)日：2022-09-15
申请号：US17828905
申请日：2022-05-31
Applicant: SanDisk Technologies LLC
Inventor： Ward Parkinson , James O'Toole , Nathan Franklin , Thomas Trent
IPC: G11C11/16
Abstract: A control circuit is configured to connect to a cross-point memory array in which each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET in a conductive state while the nMOSFET is in a non-conductive state. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be in a conductive state.
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公开(公告)号：US11222678B1
公开(公告)日：2022-01-11
申请号：US17061836
申请日：2020-10-02
Applicant: SanDisk Technologies LLC
Inventor： Ward Parkinson , James O'Toole , Nathan Franklin , Thomas Trent
Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM device, is connected in series with a threshold switching selector, such as an ovonic threshold switch. In a two-layer cross-point structure with such memory cells, the MRAM devices in one layer are inverted relative to the MRAM devices in the other layer. This can allow for the transient voltage spike placed across the MRAM device when the threshold switching selector first turns on in a sensing operation to dissipate more rapidly, reducing the risk of changing a stored data state before it can be sensed.
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公开(公告)号：US12205638B2
公开(公告)日：2025-01-21
申请号：US17939818
申请日：2022-09-07
Applicant: SanDisk Technologies LLC
Inventor： Nathan Franklin , Ward Parkinson , Michael Grobis , James O'Toole
Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.
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公开(公告)号：US11972787B2
公开(公告)日：2024-04-30
申请号：US17824806
申请日：2022-05-25
Applicant: SanDisk Technologies LLC
Inventor： Michael Nicolas Albert Tran , Michael K. Grobis , Ward Parkinson , Nathan Franklin
CPC classification number: G11C11/1659 , G06F11/1044 , G11C11/161 , G11C11/1673 , G11C11/1675
Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.
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公开(公告)号：US20230101414A1
公开(公告)日：2023-03-30
申请号：US17552143
申请日：2021-12-15
Applicant: SanDisk Technologies LLC
Inventor： Martin Hassner , Michael Nicolas Albert Tran , Ward Parkinson , Michael Grobis , Nathan Franklin , Raj Ramanujan
Abstract: Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the first ECC mode (for a given raw bit error rate (RBER)). However, the RBER may be lower when using the second ECC mode. Therefore, the first and second ECC modes may result in about the same probability of an undetectable error (or mis-correction).
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