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公开(公告)号：US07592654B2
公开(公告)日：2009-09-22
申请号：US11940569
申请日：2007-11-15
IPC分类号： H01L31/062 , H01L31/113 , H01L27/14 , H01L31/00 , H01L31/0232 , H01L27/15 , H01L29/26 , H01L31/12 , H01L33/00 , H01L29/417 , H01L29/732 , H01L27/148
CPC分类号： H01L27/14687 , H01L27/1463 , H01L27/14649
摘要： CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor also includes at least one of a horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer, and a plurality of lateral barrier layers between adjacent ones of the plurality of pixels for preventing lateral diffusion of electrons in the epitaxial layer.
摘要翻译： 具有高灵敏度和低串扰的CMOS图像传感器，特别是在远红外到红外波长的CMOS图像传感器以及CMOS图像传感器的制造方法。 CMOS图像传感器具有衬底，衬底上方的外延层以及延伸到用于接收光的外延层的多个像素。 图像传感器还包括在衬底和外延层之间的水平阻挡层中的至少一个，用于防止在衬底中产生的载流子移动到外延层，以及在多个像素中的相邻像素之间的多个横向势垒层， 防止电子在外延层中的横向扩散。
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公开(公告)号：US07307327B2
公开(公告)日：2007-12-11
申请号：US11197004
申请日：2005-08-04
IPC分类号： H01L31/00
CPC分类号： H01L27/14687 , H01L27/1463 , H01L27/14649
摘要： CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor also includes at least one of a horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer, and a plurality of lateral barrier layers between adjacent ones of the plurality of pixels for preventing lateral diffusion of electrons in the epitaxial layer.
摘要翻译： 具有高灵敏度和低串扰的CMOS图像传感器，特别是在远红外到红外波长的CMOS图像传感器以及CMOS图像传感器的制造方法。 CMOS图像传感器具有衬底，衬底上方的外延层以及延伸到用于接收光的外延层中的多个像素。 图像传感器还包括在衬底和外延层之间的水平阻挡层中的至少一个，用于防止在衬底中产生的载流子移动到外延层，以及在多个像素中的相邻像素之间的多个横向势垒层， 防止电子在外延层中的横向扩散。
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3.发明授权Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses 有权具有不同构造的源极/漏极延伸部分，晕圈和栅介质厚度的类似极性场效应晶体管的结构和制造公开(公告)号：US08377768B2
公开(公告)日：2013-02-19
申请号：US13293096
申请日：2011-11-09
申请人： Constantin Bulucea , William D. French , Donald M. Archer , Jeng-Jiun Yang , Sandeep R. Bahl , D. Courtney Parker
发明人： Constantin Bulucea , William D. French , Donald M. Archer , Jeng-Jiun Yang , Sandeep R. Bahl , D. Courtney Parker
IPC分类号： H01L21/8238
CPC分类号： H01L29/1083 , H01L21/26513 , H01L21/2652 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/823892 , H01L27/088 , H01L27/0922 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/105 , H01L29/518 , H01L29/66659 , H01L29/7835
摘要： A group of high-performance like-polarity insulated-gate field-effect transistors (100, 108, 112, 116, 120, and 124 or 102, 110, 114, 118, 122, and 126) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.
摘要翻译： 一组高性能类似极性的绝缘栅场效应晶体管（100,108,112,116,120和124或102,110,114,118,122和126）具有可选择地不同的侧向源 /漏极延伸，光晕口和栅介质厚度，适用于为模拟和/或数字应用提供各种晶体管的半导体制造平台。 每个晶体管具有一对源极/漏极区，栅极介电层和栅电极。 每个源极/漏极区域包括主要部分和更轻掺杂的横向延伸部分。 一个晶体管的一个源极/漏极区域的横向延伸比另一个晶体管的源极/漏极区域之一的横向延伸更深地掺杂或/并且在上部半导体表面之下更深地延伸。
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4.发明申请Configuration and fabrication of semiconductor structure in which source and drain extensions of field-effect transistor are defined with different dopants 有权半导体结构的配置和制造，其中场效应晶体管的源极和漏极扩展由不同掺杂剂定义公开(公告)号：US20100244150A1
公开(公告)日：2010-09-30
申请号：US12382972
申请日：2009-03-27
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L21/26513 , H01L21/26586 , H01L21/82285 , H01L21/823807 , H01L21/823814 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/167 , H01L29/6659 , H01L29/66659
摘要： An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is then more lightly doped than, and defined with dopant of higher atomic weight, than the lateral extension of the drain.
摘要翻译： 沿着半导体主体的上表面设置的绝缘栅场效应晶体管（100）包含由沟道区（244）横向隔开的一对源极/漏极区（240和242）。 栅电极（262）覆盖沟道区上方的栅介电层（260）。 每个源极/漏极区域包括与主要部分横向连续并在栅电极下方横向延伸的主要部分（240M或242M）和更轻掺杂的侧向延伸部（240E或242E）。 沿着上半导体表面终止沟道区的横向延伸部分分别由不同原子量的一对半导体掺杂剂限定。 在晶体管是非对称器件的情况下，源极/漏极区域构成源极和漏极。 源极的横向延伸比起漏极的横向延伸稍微掺杂，并且由原子量较高的掺杂剂限定。
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公开(公告)号：US07247885B2
公开(公告)日：2007-07-24
申请号：US11137939
申请日：2005-05-26
申请人： Glenn H. Rankin , Sandeep R. Bahl
发明人： Glenn H. Rankin , Sandeep R. Bahl
IPC分类号： H01L27/15
CPC分类号： H01L33/025 , H01L33/0008 , H01L33/0054 , H01L33/34
摘要： In one aspect, a first region that includes a first Group IV semiconductor that has a bandgap and is doped with a first dopant of a first electrical conductivity type is formed. A pattern is created. The pattern controls formation of local crystal modifications in the first Group IV semiconductor in an array. An array of local crystal modifications is formed in the first Group IV semiconductor in accordance with the pattern. The local crystal modifications induce overlapping strain fields that increase the bandgap of the first Group IV semiconductor, create an energy band barrier against transport of minority carriers across the first region. A second region that includes a second Group IV semiconductor that has a bandgap and is doped with a second dopant of a second electrical conductivity type opposite the first conductivity type is formed. Semiconductor devices formed in accordance with this method also are described.
摘要翻译： 一方面，形成包括具有带隙并掺杂有第一导电类型的第一掺杂物的第一IV族半导体的第一区域。 创建模式。 该图案控制阵列中第一组IV半导体中局部晶体修饰的形成。 根据图案，在第一组IV半导体中形成局部晶体修改阵列。 局部晶体修饰引起叠加的应变场，其增加第一组IV半导体的带隙，从而产生抵抗少数载流子跨越第一区域传输的能带屏障。 形成第二区域，其包括具有带隙并掺杂有与第一导电类型相反的第二导电类型的第二掺杂剂的第二IV族半导体。 还描述了根据该方法形成的半导体器件。
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6.发明授权Ohmic contact schemes for group III-V devices having a two-dimensional electron gas layer 有权具有二维电子气体层的III-V族元件的欧姆接触方案公开(公告)号：US08946780B2
公开(公告)日：2015-02-03
申请号：US13037974
申请日：2011-03-01
IPC分类号： H01L21/285 , H01L21/02 , H01L29/45 , H01L29/778 , H01L29/417 , H01L29/66 , H01L29/20
CPC分类号： H01L29/7787 , H01L21/28587 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/66462
摘要： A semiconductor device includes a first layer and a second layer over the first layer. The first and second layers are configured to form an electron gas layer at an interface of the first and second layers. The semiconductor device also includes an Ohmic contact and multiple conductive vias through the second layer. The conductive vias are configured to electrically couple the Ohmic contact to the electron gas layer. The conductive vias could have substantially vertical sidewalls or substantially sloped sidewalls, or the conductive vias could form a nano-textured surface on the Ohmic contact. The first layer could include Group III-nitride nucleation, buffer, and channel layers, and the second layer could include a Group III-nitride barrier layer.
摘要翻译： 半导体器件包括在第一层上的第一层和第二层。 第一层和第二层被配置为在第一层和第二层的界面处形成电子气层。 半导体器件还包括通过第二层的欧姆接触和多个导电通孔。 导电通孔被配置为将欧姆接触电耦合到电子气体层。 导电通孔可以具有基本上垂直的侧壁或基本上倾斜的侧壁，或者导电通孔可以在欧姆接触件上形成纳米纹理表面。 第一层可以包括III族氮化物成核，缓冲层和沟道层，第二层可以包括III族氮化物阻挡层。
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7.发明授权Configuration and fabrication of semiconductor structure in which source and drain extensions of field-effect transistor are defined with different dopants 有权半导体结构的配置和制造，其中场效应晶体管的源极和漏极扩展由不同掺杂剂定义公开(公告)号：US08304320B2
公开(公告)日：2012-11-06
申请号：US13100192
申请日：2011-05-03
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/7835 , H01L21/26513 , H01L21/26586 , H01L21/82285 , H01L21/823807 , H01L21/823814 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/167 , H01L29/6659 , H01L29/66659
摘要： An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is then more lightly doped than, and defined with dopant of higher atomic weight, than the lateral extension of the drain.
摘要翻译： 沿着半导体主体的上表面设置的绝缘栅场效应晶体管（100）包含由沟道区（244）横向隔开的一对源极/漏极区（240和242）。 栅电极（262）覆盖沟道区上方的栅介电层（260）。 每个源极/漏极区域包括与主要部分横向连续并在栅电极下方横向延伸的主要部分（240M或242M）和更轻掺杂的侧向延伸部（240E或242E）。 沿着上半导体表面终止沟道区的横向延伸部分分别由不同原子量的一对半导体掺杂剂限定。 在晶体管是非对称器件的情况下，源极/漏极区域构成源极和漏极。 源极的横向延伸比起漏极的横向延伸稍微掺杂，并且由原子量较高的掺杂剂限定。
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8.发明授权Fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone 有权具有不对称场效应晶体管的半导体结构的制造，沿着源/漏区具有定制的口袋部分公开(公告)号：US08163619B2
公开(公告)日：2012-04-24
申请号：US12382967
申请日：2009-03-27
IPC分类号： H01L21/336
CPC分类号： H01L29/7835 , H01L21/26513 , H01L21/2652 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823892 , H01L27/0922 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/665 , H01L29/66659
摘要： An asymmetric insulated-gate field effect transistor (100U or 102U) is provided along an upper surface of a semiconductor body so as to have first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima at respective locations (PH-1-PH-3-NH-3) spaced apart from one another. This typically enables the transistor to have reduced current leakage.
摘要翻译： 沿着半导体主体的上表面设置非对称绝缘栅场效应晶体管（100U或102U），以便具有由沟道区横向隔开的第一和第二源/漏区（240和242或280和282） 244或284）晶体管的主体材料。 栅电极（262或302）覆盖在沟道区上方的栅介电层（260或300）。 比主体材料的横向相邻材料更重掺杂的主体材料的口袋部分（250或290）在很大程度上仅延伸到第一个S / D区域并进入通道区域。 口袋部分的垂直掺杂剂轮廓被调整为在彼此间隔开的相应位置（PH-1-PH-3-NH-3）处达到多个局部最大值。 这通常使得晶体管具有减小的电流泄漏。
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9.发明申请Configuration and fabrication of semiconductor structure having extended-drain field-effect transistor 审中-公开具有扩展漏极场效应晶体管的半导体结构的配置和制造公开(公告)号：US20100244152A1
公开(公告)日：2010-09-30
申请号：US12382976
申请日：2009-03-27
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26513 , H01L21/2652 , H01L21/2658 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823892 , H01L27/0922 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： An extended-drain insulated-gate field-effect transistor (104 or 106) contains first and second source/drain zones 324 and 184B or 364 and 186B) laterally separated by a channel (322 or 362) zone constituted by part of a first well region (184A or 186A). A gate dielectric layer (344 or 384) overlies the channel zone. A gate electrode (346 or 386) overlies the gate dielectric layer above the channel zone. The first source/drain zone is normally the source. The second S/D zone, normally the drain, is constituted with a second well region (184B or 186B). A well-separating portion 186A or 186B/212U) of the semiconductor body extends between the well regions and is more lightly doped than each well region. The configuration of the well regions cause the maximum electric field in the IGFET's portion of the semiconductor body to occur well below the upper semiconductor surface, typically at or close to where the well regions are closest to each other. The IGFET's operating characteristics are stable with operational time.
摘要翻译： 扩展漏极绝缘栅场效应晶体管（104或106）包含由第一阱的一部分构成的沟道（322或362）区域横向隔开的第一和第二源/漏区324和184B或364和186B， 区域（184A或186A）。 栅极电介质层（344或384）覆盖在沟道区上。 栅电极（346或386）覆盖沟道区上方的栅介质层。 第一个源/漏区通常是源。 第二S / D区（通常为漏极）由第二阱区（184B或186B）构成。 半导体本体的阱分离部分186A或186B / 212U）在阱区之间延伸，并且比每个阱区域轻掺杂。 阱区域的配置导致半导体本体的IGFET的部分中的最大电场远低于上半导体表面，通常处于或接近阱区彼此最接近的位置。 IGFET的运行特性在运行时间稳定。
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10.发明申请Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portions along source/drain zone 有权具有不对称场效应晶体管的半导体结构的配置和制造，沿着源/漏区具有定制的口袋部分公开(公告)号：US20100244147A1
公开(公告)日：2010-09-30
申请号：US12382967
申请日：2009-03-27
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L21/26513 , H01L21/2652 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823892 , H01L27/0922 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/665 , H01L29/66659
摘要： An asymmetric insulated-gate field effect transistor (100U or 102U) provided along an upper surface of a semiconductor body contains first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima (316-1-316-3) at respective locations (PH-1-PH-3) spaced apart from one another. The tailoring is typically implemented so that the vertical dopant profile of the pocket portion is relatively flat near the upper semiconductor surface. As a result, the transistor has reduced leakage current.
摘要翻译： 沿着半导体主体的上表面设置的非对称绝缘栅场效应晶体管（100U或102U）包含由沟道区（244或284）横向隔开的第一和第二源/漏区（240和242或280和282） 的晶体管的主体材料。 栅电极（262或302）覆盖在沟道区上方的栅介电层（260或300）。 比主体材料的横向相邻材料更重掺杂的主体材料的口袋部分（250或290）在很大程度上仅延伸到第一个S / D区域并进入通道区域。 口袋部分的垂直掺杂剂轮廓被调整为在彼此间隔开的相应位置（PH-1-PH-3）处达到多个局部最大值（316-1-316-3）。 通常实施定制，使得袋部分的垂直掺杂剂分布在上半导体表面附近相对平坦。 结果，晶体管具有减小的漏电流。
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