公开(公告)号：US07617338B2

公开(公告)日：2009-11-10

申请号：US11050040

申请日：2005-02-03

申请人： Sang Hoo Dhong ,  Brian King Flachs ,  Harm Peter Hofstee ,  Osamu Takahashi

发明人： Sang Hoo Dhong ,  Brian King Flachs ,  Harm Peter Hofstee ,  Osamu Takahashi

IPC分类号： G06F13/28 ,  G06F5/00

CPC分类号： G06F13/28 ,  G06F13/1626 ,  G06F13/1663

摘要： A system for a processor with memory with combined line and word access is presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.

摘要翻译： 提出了一种具有组合线和字访问的存储器的处理器的系统。 系统执行窄读/写存储器访问，并使用多路复用器和锁存器对相同存储体进行宽读/写存储器存取以指导数据。 该系统使用窄读/写存储器访问处理16字节加载/请求请求，并使用宽读/写存储器访问处理128字节的DMA和指令提取请求。 在DMA请求期间，系统在一个指令周期内将16个DMA操作写入/读取存储器。 通过这样做，内存可用于在十五个其他指令周期内处理加载/存储或指令提取请求。

公开(公告)号：US06600959B1

公开(公告)日：2003-07-29

申请号：US09498934

申请日：2000-02-04

申请人： Paula Kristine Coulman ,  Sang Hoo Dhong ,  Brian King Flachs ,  Harm Peter Hofstee ,  Jaehong Park ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi

发明人： Paula Kristine Coulman ,  Sang Hoo Dhong ,  Brian King Flachs ,  Harm Peter Hofstee ,  Jaehong Park ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi

IPC分类号： G05B1918

CPC分类号： H03K17/693 ,  H03K5/06

摘要： A method and apparatus for using dynamic programmable logic arrays in microprocessor control logic provide decreased power and increased clock frequencies for data processing systems, by using programmable logic arrays exclusively for the control logic. The method and apparatus further simplify the design of the control logic and closure of timing within the microprocessor, by providing overlap of control logic evaluations and data transfers within the microprocessor.

摘要翻译： 在微处理器控制逻辑中使用动态可编程逻辑阵列的方法和装置通过专门用于控制逻辑的可编程逻辑阵列来为数据处理系统提供降低的功率和增加的时钟频率。 该方法和装置通过在微处理器内提供控制逻辑评估和数据传输的重叠来进一步简化控制逻辑的设计和微处理器内的定时闭合。

公开(公告)号：US20080189670A1

公开(公告)日：2008-08-07

申请号：US12060768

申请日：2008-04-01

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi ,  Dieter F. Wendel

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi ,  Dieter F. Wendel

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.

摘要翻译： 可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。 电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。 限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。 一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。

公开(公告)号：US07363609B2

公开(公告)日：2008-04-22

申请号：US09915437

申请日：2001-07-26

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi ,  Dieter F. Wendel

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi ,  Dieter F. Wendel

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.

摘要翻译： 可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。 电路设计方法包括首先定义逻辑合成块（16），然后执行用于要实现的预定逻辑运算的逻辑合成（17）。 限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计（29），其必须包括一系列与单个复位信号相关联的动态电路块。 一旦产生中间电路（29），电路设计方法包括从中间电路（29）消除不必要的装置（46）以产生最终的逻辑电路，然后对最终电路中的装置（48）进行尺寸调整以完成 设计。

公开(公告)号：US08136061B2

公开(公告)日：2012-03-13

申请号：US12060768

申请日：2008-04-01

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi ,  Dieter F. Wendel

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi ,  Dieter F. Wendel

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.

摘要翻译： 可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。 电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。 限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。 一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。

公开(公告)号：US06717882B1

公开(公告)日：2004-04-06

申请号：US10273590

申请日：2002-10-17

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Shoji Onishi ,  Osamu Takahashi

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Shoji Onishi ,  Osamu Takahashi

IPC分类号： G11C800

CPC分类号： G11C8/16

摘要： An improved cell circuit for data readout for use in a multiport memory is provided. The multiport memory stores write data signals. The cell circuit includes a plurality of multiplexers each coupled to a discharge device. Each of the multiplexers receives a subset of the write data signals and a plurality of read wordline signals and selects an output enable signal among the subset of the write data signals based on the read wordline signals. Each of the discharge devices are coupled to one of the multiplexers for receiving the output enable signal to generate a drive signal for driving one or more bitlines of the multiport memory.

摘要翻译： 提供用于多端口存储器中的用于数据读出的改进的单元电路。 多端口存储器存储写入数据信号。 电池电路包括多个多路复用器，每个多路复用器耦合到放电装置。 每个多路复用器接收写入数据信号的子集和多个读取字线信号，并且基于所读取的字线信号在写入数据信号的子集中选择输出使能信号。 每个放电装置耦合到多路复用器中的一个，用于接收输出使能信号，以产生用于驱动多端口存储器的一个或多个位线的驱动信号。

公开(公告)号：US06502224B2

公开(公告)日：2002-12-31

申请号：US09833413

申请日：2001-04-12

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi ,  Dieter F. Wendel

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi ,  Dieter F. Wendel

IPC分类号： G06F1750

CPC分类号： G06F17/505 ,  G06F17/5054 ,  Y02T10/82

摘要： A method and apparatus for synthesizing logic circuits with synchronized outputs is disclosed. A logic designer selects a fixed number of levels in which to synthesize the circuit, each level implementing a plurality of different logic function all having the same propagation delay. Circuit outputs are synchronized by ensuring that each logic function is synthesized by connecting logic functions from level to level such that each signal path passes through each level once and only once.

摘要翻译： 公开了一种用于合成具有同步输出的逻辑电路的方法和装置。 逻辑设计者选择固定数量的电平来合成电路，每个级别实现多个具有相同传播延迟的不同逻辑功能。 通过确保每个逻辑功能通过将逻辑功能从电平连接到电平来合成，使得每个信号路径通过每个级别一次且仅一次，从而同步电路输出。

公开(公告)号：US06826110B2

公开(公告)日：2004-11-30

申请号：US10273567

申请日：2002-10-17

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Shoji Onishi ,  Osamu Takahashi

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Shoji Onishi ,  Osamu Takahashi

IPC分类号： G11C800

CPC分类号： G11C8/16

摘要： An improved cell circuit for data readout with reduced number of read wordlines is provided in a memory block of a multiport memory array. The number of read wordlines is significantly reduced by using a decoder between the read wordlines and a multiplexer in the cell circuit. The memory block has a plurality of address inputs and stores a plurality of write data signals. In the cell circuit, the decoder receives as decoder inputs a subset of the address inputs and outputs a plurality of select signals. The multiplexer is coupled to the decoder to receive the select signals and select one of the write data signals based on the select signals. Additionally, the read wordlines are coupled to the decoder for carrying the subset of the address inputs to the decoder.

摘要翻译： 在多端口存储器阵列的存储器块中提供用于具有减少读取字线数量的数据读出的改进的单元电路。 通过在读取的字线和单元电路中的多路复用器之间使用解码器来显着减少读取字线的数量。 存储块具有多个地址输入并存储多个写入数据信号。 在单元电路中，解码器接收地址输入的子集作为解码器输入并输出多个选择信号。 复用器耦合到解码器以接收选择信号，并且基于选择信号选择写入数据信号之一。 此外，读取的字线被耦合到解码器，用于将地址输入的子集携带到解码器。

公开(公告)号：US06430672B1

公开(公告)日：2002-08-06

申请号：US09617829

申请日：2000-07-17

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Osamu Takahashi ,  Jan van Lunteren

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Osamu Takahashi ,  Jan van Lunteren

IPC分类号： G06F1210

CPC分类号： G06F12/0607 ,  G06F12/0292

摘要： A method for performing address mapping for a memory within a computer system is disclosed. The memory is organized in multiple of memory banks, and each memory bank is identified by a respective bank number. A block address portion of a physical address is translated to a corresponding bank number and an associated internal bank address. The bank number is formed by concatenating an output from a first lookup table and an output from a second lookup table. The output from the first lookup table is obtained by a first and a second segments of the block address portion, while the output from the second lookup table is obtained by a third and a fourth segments of the block address portion. Data stored in a specific location within the memory banks can be accessed by the bank number and the associated internal bank address.

摘要翻译： 公开了一种用于对计算机系统内的存储器执行地址映射的方法。 存储器组织在多个存储体中，并且每个存储体由相应的存储体号标识。 物理地址的块地址部分被转换为对应的银行号码和相关联的内部银行地址。 通过连接来自第一查找表的输出和来自第二查找表的输出来形成库号。 来自第一查找表的输出由块地址部分的第一和第二段获得，而来自第二查找表的输出由块地址部分的第三和第四段获得。 可以通过银行号码和相关联的内部银行地址访问存储在存储体中的特定位置的数据。

公开(公告)号：US07318182B2

公开(公告)日：2008-01-08

申请号：US11002692

申请日：2004-12-02

申请人： Louis Bernard Bushard ,  Sang Hoo Dhong ,  Brian King Flachs ,  Osamu Takahashi ,  Michael Brian White

发明人： Louis Bernard Bushard ,  Sang Hoo Dhong ,  Brian King Flachs ,  Osamu Takahashi ,  Michael Brian White

IPC分类号： G01R31/28

CPC分类号： G11C29/08 ,  G11C7/20 ,  G11C2029/0407

摘要： The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received initialization commands. The memory array initialization settings are stored in a memory array. A deterministic read output function for the memory array is identified and a logic built-in self test scan on the memory array is performed based on the identified deterministic read output function.

摘要翻译： 本发明提供了一种用于存储器阵列校验的方法。 接收初始化命令，并根据接收到的初始化命令生成内存阵列初始化设置。 存储器阵列初始化设置存储在存储器阵列中。 识别存储器阵列的确定性读输出功能，并且基于所识别的确定性读输出功能来执行存储器阵列上的逻辑内置自检扫描。