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9 条记录 (耗时 0.016 秒)

    Duty cycle correction circuit of DLL circuit
    1.
    发明申请
    Duty cycle correction circuit of DLL circuit 有权
    DLL电路的占空比校正电路

    公开(公告)号：US20060267649A1

    公开(公告)日：2006-11-30

    申请号：US11320832

    申请日：2005-12-30

    申请人： Sang Park ,  Min You

    发明人： Sang Park ,  Min You

    IPC分类号： H03L7/06

    CPC分类号： H03K5/1565

    摘要： The present invention relates to a duty cycle correction circuit of a DLL circuit. According to the present invention, in an APDM, a voltage comparator of a duty cycle correction circuit operates without being reset. Therefore, although an internal power supply voltage is instantly changed in the APDM, the duty cycle of a DLL clock can be accurately set to 50%.

    摘要翻译： 本发明涉及一种DLL电路的占空比校正电路。 根据本发明，在APDM中，占空比校正电路的电压比较器在不复位的情况下运行。 因此，虽然在APDM内部电源电压立即变化，但是可以将DLL时钟的占空比精确地设定为50％。

    X address extractor and method for extracting X-address in memory device
    2.
    发明申请
    X address extractor and method for extracting X-address in memory device 失效
    X地址提取器及其在存储器件中提取X地址的方法

    公开(公告)号：US20050128856A1

    公开(公告)日：2005-06-16

    申请号：US10878443

    申请日：2004-06-28

    申请人： Min You

    发明人： Min You

    IPC分类号： G11C8/00 ,  G11C8/18 ,  G11C11/408

    CPC分类号： G11C11/4087 ,  G11C8/18

    摘要： The disclosed is a memory such DRAM (dynamic random access memory), particularly an X-address extractor, an X-address extraction method and a memory adaptable to a high speed operation. A DRAM receives X and Y-addresses through an address line. The X-address is input through a command line when an active command is input to the DRAM, and the Y-address is input when a read/write command is input to the DRAM. The X-address abstractor performs a function of extracting the X-address from the X and Y addresses transferred through the address line. A conventional X-address extractor has a problem that the X-address has a different value when a selection signal changes to logic ‘0’ from logic ‘1’ after an address signal changes to another value from an X-address. The present X-address extractor includes a selection signal generator, a delayer, a latch and an X-address switch, without the problem of the conventional art.

    摘要翻译： 所公开的是诸如DRAM（动态随机存取存储器），特别是X地址提取器，X地址提取方法和适于高速操作的存储器的存储器。 DRAM通过地址线接收X和Y地址。 当将有效命令输入到DRAM时，通过命令行输入X地址，并且当向DRAM输入读/写命令时，输入Y地址。 X地址抽象器执行从通过地址线传送的X和Y地址提取X地址的功能。 常规的X地址提取器存在一个问题，当地址信号从X地址变为另一个值之后，当选择信号从逻辑“1”变为逻辑“0”时，X地址具有不同的值。 当前的X地址提取器包括选择信号发生器，延迟器，锁存器和X地址开关，而没有现有技术的问题。

    Memory device and test method thereof
    3.
    发明申请
    Memory device and test method thereof 失效
    存储器件及其测试方法

    公开(公告)号：US20060072362A1

    公开(公告)日：2006-04-06

    申请号：US11008273

    申请日：2004-12-10

    申请人： Min You

    发明人： Min You

    IPC分类号： G11C7/00

    CPC分类号： G11C29/14 ,  G11C2029/1204

    摘要： A memory device and a test method thereof enable verification of fail of a cell region by intercepting bit lines connected to the cell region in a write-verify-read test. The memory device comprises a plurality of bit line switches and a separation control unit. The bit line switches connect the bit lines of the bit line sense amplifier to those of the selected cell array in response to a bit line separation control signal in a normal mode, separate the bit lines of the bit line sense amplifier from those of the unselected cell array, and separate the bit lines of the bit line sense amplifier from those of the cell array in response to the bit line separation control signal in a test mode. The separation control unit disables the bit line separation control signal in response to a test mode signal in the test mode.

    摘要翻译： 存储器件及其测试方法通过在写入验证读取测试中截取连接到单元区域的位线来验证单元区域的故障。 存储装置包括多个位线开关和分离控制单元。 位线开关响应于正常模式中的位线分离控制信号将位线读出放大器的位线连接到所选单元阵列的位线，将位线读出放大器的位线与未选择的单元阵列的位线分开 单元阵列，并且在测试模式中响应于位线分离控制信号，将位线读出放大器的位线与单元阵列的位线分开。 分离控制单元响应于测试模式下的测试模式信号而禁用位线分离控制信号。

    Semiconductor Device
    5.
    发明申请
    Semiconductor Device 失效
    半导体器件

    公开(公告)号：US20070083696A1

    公开(公告)日：2007-04-12

    申请号：US11458208

    申请日：2006-07-18

    申请人： Min You

    发明人： Min You

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0207 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4093 ,  G11C29/1201

    摘要： A semiconductor device may include a decoder for decoding a plurality of internal command signals and outputting a first Y-address enabling signal; a Y-address enabling signal generator for receiving the first Y-address enabling signal and outputting a second Y-address enabling signal having a predetermined enabled period; a multiplexer (MUX) for receiving the first Y-address enabling signal and the second Y-address enabling signal and selectively outputting any one thereof as a Y-address enabling signal; and a MUX controller for controlling the MUX such that the MUX selects any one of the first Y-address enabling signal or second Y-address enabling signal according to an operation mode of the semiconductor device.

    摘要翻译： 半导体器件可以包括用于对多个内部命令信号进行解码并输出第一Y地址使能信号的解码器; Y地址使能信号发生器，用于接收第一Y地址使能信号并输出​​具有预定使能周期的第二Y地址使能信号; 用于接收第一Y地址使能信号和第二Y-地址使能信号的多路复用器（MUX），并选择性地输出任何一个作为Y地址使能信号; 以及MUX控制器，用于控制MUX，使得MUX根据半导体器件的操作模式选择第一Y地址使能信号或第二Y地址使能信号中的任何一个。

    Column selection signal generator of semiconductor memory device
    7.
    发明申请
    Column selection signal generator of semiconductor memory device 失效
    半导体存储器件的列选择信号发生器

    公开(公告)号：US20060209602A1

    公开(公告)日：2006-09-21

    申请号：US11148561

    申请日：2005-06-09

    申请人： Min You

    发明人： Min You

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1048 ,  G11C2207/002

    摘要： A column selection signal generator of a semiconductor memory device is configured to maintain a predetermined pulse width of a column selection signal regardless of change in process and external conditions by selectively using a self-generated pulse signal and a pulse signal generated by an external clock signal. The column selection signal generator comprises a command combination unit, a pulse generating unit, a comparison unit and a selection unit.

    摘要翻译： 半导体存储器件的列选择信号发生器被配置为通过选择性地使用自产生的脉冲信号和由外部时钟信号产生的脉冲信号来保持列选择信号的预定脉冲宽度，而不管处理和外部条件的变化 。 列选择信号发生器包括命令组合单元，脉冲发生单元，比较单元和选择单元。

    X address extractor and memory for high speed operation
    8.
    发明申请
    X address extractor and memory for high speed operation 有权
    X地址提取器和内存，用于高速运行

    公开(公告)号：US20050128857A1

    公开(公告)日：2005-06-16

    申请号：US10878824

    申请日：2004-06-28

    申请人： Min You

    发明人： Min You

    IPC分类号： G11C8/10 ,  G11C11/408 ,  G11C7/00

    CPC分类号： G11C11/408 ,  G11C8/10

    摘要： The disclosed is a memory such DRAM (dynamic random access memory), particularly an X-address extractor, an X-address extraction method and a memory adaptable to a high speed operation. A DRAM receives X and Y-addresses through an address line. The X-address is input through a command line when an active command is input to the DRAM, and the Y-address is input when a read/write command is input to the DRAM. The X-address abstractor performs a function of extracting the X-address from the X and Y addresses transferred through the address line. A conventional X-address extractor has a problem that the X-address has a different value when a selection signal changes to logic ‘0’ from logic ‘1’ after an address signal changes to another value from an X-address. The present X-address extractor includes a selection signal generator, a delayer, a latch and an X-address switch, without the problem of the conventional art.

    摘要翻译： 所公开的是诸如DRAM（动态随机存取存储器），特别是X地址提取器，X地址提取方法和适于高速操作的存储器的存储器。 DRAM通过地址线接收X和Y地址。 当将有效命令输入到DRAM时，通过命令行输入X地址，并且当向DRAM输入读/写命令时，输入Y地址。 X地址抽象器执行从通过地址线传送的X和Y地址提取X地址的功能。 常规的X地址提取器存在一个问题，当地址信号从X地址变为另一个值之后，当选择信号从逻辑“1”变为逻辑“0”时，X地址具有不同的值。 当前的X地址提取器包括选择信号发生器，延迟器，锁存器和X地址开关，而没有现有技术的问题。

    Refresh controller with low peak current
    9.
    发明申请
    Refresh controller with low peak current 失效
    刷新控制器具有低峰值电流

    公开(公告)号：US20050128847A1

    公开(公告)日：2005-06-16

    申请号：US10874568

    申请日：2004-06-22

    申请人： Min You

    发明人： Min You

    IPC分类号： G11C7/00 ,  G11C11/406

    CPC分类号： G11C11/406 ,  G11C2211/4067

    摘要： The disclosure relates to a memory such as a DRAM (dynamic random access memory), specifically to a refresh controller embedded in a memory. The refresh controller according to the present invention lowers the levels of peak currents by differentiating active times of a first bank enable signal and a second bank enable signal. The present invention has an advantage that there is no problem of substantially reducing a refresh prosecution time for a second portion because a delayed refresh enable signal is being disabled even while the second bank enable signal is being enabled.

    摘要翻译： 本公开涉及诸如DRAM（动态随机存取存储器）的存储器，具体涉及嵌入在存储器中的刷新控制器。 根据本发明的刷新控制器通过区分第一组使能信号和第二存储体使能信号的有效时间来降低峰值电流的电平。 本发明的优点在于，即使在启用第二存储体使能信号时，由于延迟刷新使能信号被禁止，所以不存在显着减少第二部分的刷新检测时间的问题。