公开(公告)号：US08299660B2

公开(公告)日：2012-10-30

申请号：US12144005

申请日：2008-06-23

申请人： Sang Pil Yoon ,  Jin Young Jeon ,  Yong Jae Park

发明人： Sang Pil Yoon ,  Jin Young Jeon ,  Yong Jae Park

IPC分类号： H02K5/24 ,  H02K5/00 ,  H02K5/04

CPC分类号： F16F15/08 ,  H02K5/24

摘要： A motor fixing structure and a motor assembly capable of reducing vibration of a motor and also maintaining a compact configuration. The motor assembly includes a motor, a fixing member disposed to be spaced from the motor by a predetermined spacing distance, and a vibration absorbing member to prevent vibration of the motor from being transferred to the fixing member, wherein the vibration absorbing member is formed to be longer by a predetermined specified length than the predetermined spacing distance between the motor and the fixing member and is disposed outside of a periphery of the motor.

摘要翻译： 电动机固定结构和电动机组件，其能够减少电动机的振动并且还保持紧凑的构造。 电动机组件包括电动机，与电动机隔开预定间隔距离设置的固定部件，以及用于防止电动机转动到固定部件的振动的振动吸收部件，其中振动吸收部件形成为 比电动机和固定构件之间的预定间隔距离更长预定的规定长度，并且设置在电动机的周边之外。

公开(公告)号：US06918046B2

公开(公告)日：2005-07-12

申请号：US09870585

申请日：2001-06-01

申请人： Yong Jae Park ,  Jong Doo Joo

发明人： Yong Jae Park ,  Jong Doo Joo

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  H04L7/00 ,  G06F5/06 ,  G06F13/00

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

摘要： A high speed interface type device can reduce power consumption and a circuit area, and transmit/receive a 4 bit data in one clock period. The high speed interface type device includes a DRAM unit for generating first clock and clock bar signals which do not have a phase difference from a main clock signal, and second clock and clock bar signals having 90° phase difference from the first clock and clock bar signals in a write operation, storing an inputted 4 bit data in one period of the main clock signal according to the first clock to second clock bar signals, synchronizing the stored data with data strobe signals according to the first clock to second clock bar signals in a read operation, and outputting a 4 bit data in one period of the main clock signal, and a controller for transmitting a command, address signal and data signal synchronized with the main clock signal to the DRAM unit in the write operation, and receiving data signals from the DRAM unit in the read operation.

摘要翻译： 高速接口型设备可以降低功耗和电路面积，并在一个时钟周期内发送/接收4位数据。 高速接口型设备包括用于产生第一时钟的DRAM单元和与主时钟信号不具有相位差的时钟条信号，以及与第一时钟和时钟条具有90°相位差的第二时钟和时钟条信号 写入操作中的信号，将根据第一时钟的主时钟信号的一个周期中的输入的4位数据存储到第二时钟条信号，将存储的数据与根据第一时钟的数据选通信号同步到第二时钟条信号 读操作，并在主时钟信号的一个周期内输出4位数据;以及控制器，用于在写入操作中向DRAM单元发送与主时钟信号同步的命令，地址信号和数据信号，以及接收数据 在读取操作中来自DRAM单元的信号。

公开(公告)号：US20110025002A1

公开(公告)日：2011-02-03

申请号：US12920531

申请日：2009-03-02

申请人： Yong Jae Park

发明人： Yong Jae Park

IPC分类号： A63C17/04 ,  B60B19/12

CPC分类号： A43B5/1633 ,  A63C17/008 ,  A63C17/06 ,  A63C17/20

摘要： Disclosed are a wheel assembly and wheeled shoes having the same. According to an embodiment of the invention, a wheel assembly, being installed in a way to allow wheel(s) to be retracted into or pulled out of an inner space, includes: a base block fixed in the inner space; a wheel support, to which the wheel(s) is (are) rotatably coupled and which is pivotably mounted on the base block about a first axis, thus pivoting between a first position where the wheel(s) is (are) retracted into the inner space and a second position where the wheel(s) is (are) pulled out of the inner space; and a positioner, which enables the wheel support to pivot between the first position and the second position and fixes the position of the wheel support to prevent the wheel support from pivoting on the base block when the wheel support is located in the first position or in the second position.

摘要翻译： 公开了一种车轮组件和具有该组件的轮式鞋。 根据本发明的一个实施例，一种车轮组件，其以允许轮子缩回到内部空间或从内部空间中拉出的方式安装，包括：固定在内部空间中的基座; 一个车轮支撑件，一个或多个车轮可旋转地联接到该车轮支撑件上，并且其可绕第一轴线可枢转地安装在基座上，从而在车轮（一个或多个）被缩回到第一位置的第一位置之间枢转 内部空间和第二位置，其中所述轮被从所述内部空间拉出; 以及定位器，其使得所述车轮支撑件能够在所述第一位置和所述第二位置之间枢转并且固定所述车轮支撑件的位置，以防止所述车轮支撑件在所述车轮支撑件位于所述第一位置时在所述基座上枢转，或者在 第二个位置。

公开(公告)号：US20180009602A1

公开(公告)日：2018-01-11

申请号：US15544821

申请日：2016-01-19

申请人： Yong Jae Park

发明人： Yong Jae Park

IPC分类号： B65D88/52 ,  B65D88/12 ,  B65D90/00

摘要： The present disclosure relates to a foldable container which includes a pair of side walls disposed side-by-side; a guide rail disposed in a direction transverse-crossing between lower ends of the one pair of side walls to guide movement of at least one of the side walls; an upper plate and a lower plate, wherein each of the upper plate and the lower plate is divided into at least two unit plates that are rotatably connected to each other so as to be folded by the movement of the side wall, and wherein each of the upper plate and the lower plate connects upper ends of the pair of side walls to each other and connects lower ends of the one pair of side walls to each other; and a door rotatably connected to each of a front end and a rear end of the side wall.

公开(公告)号：US06813196B2

公开(公告)日：2004-11-02

申请号：US09892549

申请日：2001-06-28

申请人： Yong Jae Park ,  Se Jun Kim

发明人： Yong Jae Park ,  Se Jun Kim

IPC分类号： G11C700

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076

摘要： The present invention discloses a high speed interface type semiconductor memory device which can transmit data of a plurality of DRAMs of a module to a controller by using only one data strobe clock signal. The high speed interface type semiconductor memory device includes a DRAM module unit for generating a strobe clock signal for synchronizing a data signal in a read operation in a DRAM farthest from a controller among a plurality of DRAMs, providing the strobe clock signal to the other DRAMs, and transmitting data to the controller in the read operation, and a controller for transmitting a clock signal and data signals synchronized with the clock signal to the plurality of DRAMs, and receiving data signals from the DRAMs.

摘要翻译： 本发明公开了一种高速接口型半导体存储器件，其可以通过仅使用一个数据选通时钟信号将模块的多个DRAM的数据传输到控制器。 高速接口型半导体存储器件包括：DRAM模块单元，用于产生用于在多个DRAM中与控制器最远的DRAM中的读取操作中的数据信号同步的选通时钟信号，将选通时钟信号提供给其它DRAM ，以及在读取操作中向控制器发送数据，以及用于将时钟信号和与时钟信号同步的数据信号发送到多个DRAM的控制器，以及从DRAM接收数据信号。

公开(公告)号：US06215722B1

公开(公告)日：2001-04-10

申请号：US09473697

申请日：1999-12-29

申请人： Yong Jae Park

发明人： Yong Jae Park

IPC分类号： G11C800

CPC分类号： G11C7/109 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076

摘要： The present invention relates to a command latency circuit for a programmable SynchLink Dynamic Random Access Memory (SLDRAM) which is an ultrahigh speed memory device. The command latency circuit for the SLDRAM includes: a command decoder unit for decoding and outputting an input of a command address; an internal clock generating unit for outputting an internal clock according to an input of a master clock while a latency is operated; a register decoder unit for receiving and decoding a register data; a burst control unit for receiving the output signal from the command decoder unit and the internal clock, and outputting a command pulse; a shift register unit for shift-outputting the output signal from the burst control unit according to an input of the internal clock; and an output unit for receiving the output signals from the shift register unit and the register decoder unit, and outputting a command signal having a wanted delay. Accordingly, the command latency circuit in accordance with the present invention can reduce the power consumption by decreasing loading of the master clock, perform a delay program by using the register, and reduce the number of the shift registers delaying the command.

摘要翻译： 本发明涉及作为超高速存储装置的可编程SynchLink动态随机存取存储器（SLDRAM）的命令延迟电路。 SLDRAM的命令延迟电路包括：命令解码器单元，用于解码并输出命令地址的输入; 内部时钟产生单元，用于在等待时间被操作时根据主时钟的输入输出内部时钟; 寄存器解码器单元，用于接收和解码寄存器数据; 突发控制单元，用于从命令解码器单元和内部时钟接收输出信号，并输出命令脉冲; 移位寄存器单元，用于根据内部时钟的输入对来自突发控制单元的输出信号进行移位输出; 以及输出单元，用于接收来自移位寄存器单元和寄存器解码器单元的输出信号，并输出具有所需延迟的指令信号。 因此，根据本发明的命令延迟电路可以通过减少主时钟的负载来减少功耗，通过使用该寄存器执行延迟程序，并减少延迟该命令的移位寄存器的数量。

公开(公告)号：US6006524A

公开(公告)日：1999-12-28

申请号：US981199

申请日：1998-04-03

申请人： Yong Jae Park

发明人： Yong Jae Park

IPC分类号： A47C21/04 ,  A47G9/02 ,  F25B21/02

CPC分类号： A47C21/048 ,  A47C21/044 ,  A47G9/0215

摘要： A temperature controller for bedding which can always provide a comfortable sleeping environment by maintaining bedding at a temperature suitable for the human body during sleeping by supplying cold or warm heat transfer medium to the inside of bedding, such as a floor mat or a bed mattress according to a preset temperature and a preset time. The temperature controller is constituted of a thermoelectric element 10 which selectively serves as a cooler or heater according to a set temperature, a controller 20 which compares the temperatures detected by means of a room temperature sensor 291, a supply temperature sensor 231 and a recovery temperature sensor 232 with set appropriate temperatures and operates the thermoelectric element 10 by outputting an output signal based on the set time of an operating time setting section 22, a heat exchanger 30 which causes heat exchange between heat exchange fins 11 cooled or heated by the thermoelectric element 10 and a heat transfer medium and supplies the heat transfer medium, and bedding 40 inside of which the heat transfer medium from the heat exchanger 30 is circulated.

摘要翻译： PCT No.PCT / KR97 / 00060 Sec。 371日期：1998年4月3日 102（e）日期1998年4月3日PCT 1997年4月18日PCT PCT。 公开号WO97 / 38607 日期1997年10月23日一种用于床上用品的温度控制器，其可以通过在睡觉期间通过向床垫内部提供冷或热传热介质来维持床上用品，从而提供舒适的睡眠环境，例如地板垫 或床垫根据预设温度和预设时间。 温度控制器由根据设定温度选择性地用作冷却器或加热器的热电元件10构成，控制器20将通过室温传感器291检测到的温度，供应温度传感器231和回收温度 传感器232具有设定的适当温度，并且通过基于操作时间设定部分22的设定时间输出输出信号来操作热电元件10;热交换器30，其在由热电元件冷却或加热的热交换翅片11之间进行热交换 10和传热介质，并且供给传热介质，并且其内部的来自热交换器30的传热介质循环的床上用品40。