公开(公告)号：US07702970B2

公开(公告)日：2010-04-20

申请号：US10695390

申请日：2003-10-29

申请人： Sang-Hyuck Ha ,  Seo-Weon Heo ,  Nam-Yul Yu ,  Min-Goo Kim ,  Seong-Woo Ahn

发明人： Sang-Hyuck Ha ,  Seo-Weon Heo ,  Nam-Yul Yu ,  Min-Goo Kim ,  Seong-Woo Ahn

IPC分类号： G06F11/00 ,  G11C29/00

CPC分类号： H04L1/0066 ,  H03M13/271 ,  H03M13/275 ,  H03M13/276 ,  H03M13/2764 ,  H04L1/0045 ,  H04L1/0071

摘要： An apparatus and method for reading written symbols by deinterleaving to decode a written encoder packet in a receiver for a mobile communication system supporting turbo coding and interleaving, such that a turbo-coded/interleaved encoder packet has a bit shift value m, an up-limit value J and a remainder R, and a stream of symbols of the encoder packet is written in order of column to row. The apparatus and method perform the operations of generating an interim address by bit reversal order (BRO) assuming that the remainder R is 0 for the received symbols; calculating an address compensation factor for compensating the interim address in consideration of a column formed with the remainder; and generating a read address by adding the interim address and the address compensation factor for a decoding-required symbol, and reading a symbol written in the generated read address.

摘要翻译： 一种用于通过解交织来读取写入的符号的装置和方法，用于解码支持turbo编码和交织的移动通信系统的接收机中的书写编码器分组，使得turbo编码/交织的编码器分组具有比特移位值m， 限制值J和余数R，并且编码器分组的符号流以列到行的顺序写入。 该装置和方法执行假设所接收的符号的余数R为0，通过比特反转顺序（BRO）生成中间地址的操作; 考虑到与其余部分形成的列，计算补偿中间地址的地址补偿因子; 以及通过添加用于解码所需符号的临时地址和地址补偿因子以及读取写入所生成的读取地址中的符号来生成读取地址。

公开(公告)号：US07505535B2

公开(公告)日：2009-03-17

申请号：US10718816

申请日：2003-11-24

申请人： Sang-Hyuck Ha ,  Nam-Yul Yu ,  Min-Goo Kim

发明人： Sang-Hyuck Ha ,  Nam-Yul Yu ,  Min-Goo Kim

IPC分类号： H03D1/00

CPC分类号： H04L1/0059 ,  H03M13/2771 ,  H03M13/2957 ,  H03M13/6566 ,  H04L1/0066 ,  H04L1/0071

摘要： A method and apparatus for effectively controlling data input to a turbo decoder for decoding forward packet data traffic in a 1xEV-DV mobile station (MS) are disclosed. After received code symbols are stored in one of several memories and read in deinterleaving order, read addresses and chip select signals are generated for the memories based on encoder packet size in synchronization to a decoder clock signal. The decoding starts by inputting a predetermined number of code symbols to the turbo decoder in an appropriate order. The decoder input apparatus reads demodulated forward packet data from decoder input buffers in an appropriate order using the read addresses and chip select signals to generate turbo decoder input data in an appropriate form. Thus, a small-size, low-cost, low-power consumption MS is achieved by processing channel-interleaved data at high speed and with reduced process delay and providing them to a decoder.

摘要翻译： 公开了一种用于有效地控制输入到turbo解码器的数据的方法和装置，用于解码1xEV-DV移动台（MS）中的前向分组数据业务。 在接收到的代码符号被存储在几个存储器中的一个并以解交错顺序读取时，基于与解码器时钟信号同步的编码器分组大小，为存储器生成读取地址和片选信号。 通过以适当的顺序向turbo解码器输入预定数量的码符号开始解码。 解码器输入装置使用读取的地址和芯片选择信号以适当的顺序从解码器输入缓冲器读取解调的前向分组数据，以适当的形式产生turbo解码器输入数据。 因此，通过以高速和减少的处理延迟处理信道交错数据并将其提供给解码器来实现小尺寸，低成本，低功耗的MS。

公开(公告)号：US07032156B2

公开(公告)日：2006-04-18

申请号：US10622508

申请日：2003-07-21

申请人： Nam-Yul Yu ,  Min-Goo Kim ,  Sang-Hyuck Ha

发明人： Nam-Yul Yu ,  Min-Goo Kim ,  Sang-Hyuck Ha

IPC分类号： H03M13/45

CPC分类号： H03M13/3905 ,  H03M13/2957 ,  H03M13/3911

摘要： An Forward Error Correction (FEC) apparatus and method for reducing Bit error rates (BER) and Frame Error Rates (FER) using turbo decoding in a digital communication system. In a constituent decoder for decoding a turbo code, a first adder calculates the LLR of a received code symbol by calculating the difference between the probability of the code symbol being 1 and that of the code symbol being 0 at an arbitrary state of a turbo decoding trellis. A second adder adds the transmission information and a priori information of the code symbol. A third adder calculates the difference between the outputs of the first and second adders as extrinsic information. A first multiplier multiplies the output of the third adder by a predetermined weighting factor as a feedback gain. A correction value calculator calculates a correction value using the difference between the best metric and the second best metric of the code symbol. A fourth adder adds the correction value to the output of the first multiplier.

摘要翻译： 一种用于在数字通信系统中使用turbo解码来降低误码率（BER）和帧错误率（FER）的前向纠错（FEC）装置和方法。 在用于解码turbo码的构成解码器中，第一加法器通过在Turbo解码的任意状态下计算代码符号为1的概率与代码符号为0的概率之间的差来计算接收到的代码符号的LLR 格子 第二加法器将传输信息和代码符号的先验信息相加。 第三加法器计算第一和第二加法器的输出之间的差作为外在信息。 第一乘法器将第三加法器的输出乘以预定的加权因子作为反馈增益。 校正值计算器使用代码符号的最佳度量和第二最佳度量之间的差来计算校正值。 第四加法器将校正值与第一乘法器的输出相加。

公开(公告)号：US07508805B2

公开(公告)日：2009-03-24

申请号：US10398369

申请日：2001-10-05

申请人： Soon-Jae Choi ,  Min-Goo Kim ,  Beong-Jo Kim ,  Young-Hwan Lee ,  Nam-Yul Yu ,  Sang-Hyuck Ha

发明人： Soon-Jae Choi ,  Min-Goo Kim ,  Beong-Jo Kim ,  Young-Hwan Lee ,  Nam-Yul Yu ,  Sang-Hyuck Ha

IPC分类号： H04B7/216 ,  H03M13/00 ,  H03M13/03 ,  H04L25/34 ,  H04L25/49

CPC分类号： H03M13/2957 ,  H03M13/09 ,  H04B1/707 ,  H04L1/0046 ,  H04L1/005 ,  H04L1/0061 ,  H04L1/0064

摘要： The present invention relates to an apparatus and method for detecting a data rate in a turbo decoder for a mobile communication system. When a rate selector selects one data rate among a plurality of data rates, a turbo decoder repeatedly decodes an input data frame within a predetermined repetition limit number using the selected data rate and outputs the decoded data. A CRC detector performs CRC check on the decoded data and outputs the CRC check result, and a decoding state measurer measures decoding quality depending on the decoded data and outputs decoding state information. A controller then sets the repetition limit number to a predetermined minimum value, controls the repetition limit number according to the decoding state information, controls the rate selector and determines a data rate of the input data depending on the CRC check result.

摘要翻译： 本发明涉及用于检测用于移动通信系统的turbo解码器中的数据速率的装置和方法。 当速率选择器选择多个数据速率中的一个数据速率时，turbo解码器使用所选择的数据速率重复地对预定重复限制数目内的输入数据帧进行解码，并输出解码数据。 CRC检测器对解码数据执行CRC校验并输出CRC校验结果，解码状态测量器根据解码数据测量解码质量并输出解码状态信息。 然后，控制器将重复限制号码设置为预定的最小值，根据解码状态信息控制重复限制号码，控制速率选择器，并根据CRC校验结果确定输入数据的数据速率。

公开(公告)号：US07349494B2

公开(公告)日：2008-03-25

申请号：US10671553

申请日：2003-09-29

申请人： Nam-Yul Yu ,  Sang-Hyuck Ha ,  Min-Goo Kim

发明人： Nam-Yul Yu ,  Sang-Hyuck Ha ,  Min-Goo Kim

IPC分类号： H04L27/00

CPC分类号： H04L1/0071 ,  H04L1/0003 ,  H04L1/007 ,  H04L1/0083 ,  H04L27/18 ,  H04L27/34

摘要： A method and apparatus for deshuffling received shuffled data in a communication system supporting multi-level modulation. A transmitter encodes information bits and shuffles code symbols so that systematic symbols having a relatively high priority are disposed at high-transmission reliability positions and parity symbols having a relatively low priority are disposed at low-transmission reliability positions in a modulation symbol. A receiver demodulates received data and outputs a modulation symbol having a plurality of code symbols, stores the code symbols separately as systematic symbols and parity symbols in corresponding memory areas according to a deshuffling order corresponding to the shuffling, reads the stored code symbols, decodes the stored code symbols at a predetermined code rate, and thus outputs an packet.

摘要翻译： 一种在支持多级调制的通信系统中对混洗数据进行混洗的方法和装置。 发送器对信息比特进行编码并混合编码符号，使得具有较高优先级的系统符号被布置在高传输可靠性位置，并且具有较低优先级的奇偶校验符号被布置在调制符号中的低传输可靠性位置。 接收机对接收到的数据进行解调并输出具有多个码符号的调制符号，根据与洗牌相对应的混洗顺序将代码符号分别存储在相应的存储区域中作为系统符号和奇偶校验符号，读出存储的码元，对 以预定的码率存储代码符号，从而输出分组。

公开(公告)号：US07249304B2

公开(公告)日：2007-07-24

申请号：US10727625

申请日：2003-12-05

申请人： Nam-Yul Yu ,  Min-Goo Kim

发明人： Nam-Yul Yu ,  Min-Goo Kim

IPC分类号： G06F11/00

CPC分类号： H04L1/0051 ,  H03M13/2957 ,  H03M13/2975

摘要： An FEC apparatus and method is provided that uses turbo codes. An input frame is iteratively decoded until an iterative decoding stop command is received under a predetermined control, and the absolute reliability of each symbol in the frame is output. The minimum of the absolute reliabilities is detected as a measurement, and a threshold is detected using the a-priori information and extrinsic information of the each symbol. The measurement is compared with the threshold, and the iterative decoding stop command is output according to the comparison result.

摘要翻译： 提供了使用turbo码的FEC装置和方法。 输入帧被迭代地解码，直到在预定控制下接收到迭代解码停止命令，并且输出帧中每个符号的绝对可靠性。 将绝对可靠度的最小值作为测量值被检测，并且使用每个符号的先验信息和外在信息来检测阈值。 将测量与阈值进行比较，并根据比较结果输出迭代解码停止命令。

公开(公告)号：US07137060B2

公开(公告)日：2006-11-14

申请号：US10458204

申请日：2003-06-11

申请人： Nam-Yul Yu ,  Min-Goo Kim

发明人： Nam-Yul Yu ,  Min-Goo Kim

IPC分类号： H03M13/03 ,  H03M13/00

CPC分类号： H03M13/658 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/112

摘要： A forward error correction method for decoding coded bits generated by low density parity check matrixes. The method comprises converting each of the coded bits into a log likelihood ratio (LLR) value, and applying the converted values to variable nodes; delivering messages applied to the variable nodes to check nodes; checking a message having a minimum value among the messages, and determining a sign of the message having the minimum value; receiving messages updated in the check nodes, adding up signs of the received messages and a sign of an initial message, applying a weighting factor of 1 when all signs are identical, and when all signs are not identical, updating a message of a variable node by applying a weighting factor; determining LLR of an initial input value; and hard-deciding values of the variable nodes, performing parity check on the hard decision values, and stopping the decoding when no error occurs.

摘要翻译： 一种用于解码由低密度奇偶校验矩阵产生的编码比特的前向纠错方法。 该方法包括将每个编码比特转换成对数似然比（LLR）值，并将转换的值应用于可变节点; 传递应用于变量节点的消息以检查节点; 检查消息中具有最小值的消息，并确定具有最小值的消息的符号; 接收在校验节点中更新的消息，将接收到的消息的符号和初始消息的符号相加，当所有符号相同时应用加权因子1，并且当所有符号不相同时，更新变量节点的消息 通过应用加权因子; 确定初始输入值的LLR; 可变节点的硬判定值，硬判决值进行奇偶校验，无错误发生时停止解码。

公开(公告)号：US07178082B2

公开(公告)日：2007-02-13

申请号：US10834069

申请日：2004-04-29

申请人： Nam-Yul Yu ,  Min-Goo Kim ,  Gang-Mi Gil

发明人： Nam-Yul Yu ,  Min-Goo Kim ,  Gang-Mi Gil

IPC分类号： H03M13/11

CPC分类号： H03M13/116 ,  H03M13/1137 ,  H03M13/118 ,  H03M13/1185

摘要： An apparatus and method for generating an encoding matrix for a low density parity check (LDPC) code having a dual-diagonal matrix as a parity check matrix are disclosed. The apparatus and method construct an information sub-matrix of the encoding matrix with a predetermined number of square matrixes according to a predetermined code rate such that each of the square matrixes has columns and rows with a weight of 1 and has a different offset value, combine the square matrixes with the dual-diagonal matrix, and perform inter-row permutation on the information sub-matrix.

摘要翻译： 公开了一种用于生成具有双对角矩阵作为奇偶校验矩阵的低密度奇偶校验（LDPC）码的编码矩阵的装置和方法。 该装置和方法根据预定的码率构建具有预定数目的方阵的编码矩阵的信息子矩阵，使得每个方阵具有权重为1的具有不同偏移值的列和行， 将平方矩阵与双对角矩阵组合，并在信息子矩阵上进行行间排列。

公开(公告)号：US20070022354A1

公开(公告)日：2007-01-25

申请号：US10563216

申请日：2004-10-14

申请人： Nam-Yul Yu ,  Min-Goo Kim

发明人： Nam-Yul Yu ,  Min-Goo Kim

IPC分类号： H03M13/00

CPC分类号： H03M13/1197 ,  H03M13/1114 ,  H03M13/1137 ,  H03M13/1162 ,  H03M13/118 ,  H03M13/1185 ,  H03M13/611

摘要： An apparatus and method for encoding low-density parity check (LDPC) codes. The method for generating a low-density parity check code formed of an information-part matrix and a parity-part matrix comprises the steps of converting the information-part matrix into an array code structure and assigning a degree sequence to each submatrix column; extending a dual-diagonal matrix corresponding to the parity-part matrix such that an offset value between diagonals has a random value; lifting the normalized dual-diagonal matrix; determining an offset value for cyclic column shift for each submatrix of the lifted normalized dual-diagonal matrix; and determining a parity symbol corresponding to a column of the parity-part matrix.

摘要翻译： 一种用于编码低密度奇偶校验（LDPC）码的装置和方法。 用于产生由信息部分矩阵和奇偶校验部分矩阵形成的低密度奇偶校验码的方法包括以下步骤：将信息部分矩阵转换为阵列码结构，并将度序列分配给每个子矩阵列; 扩展对应于奇偶校验部分矩阵的双对角矩阵，使得对角线之间的偏移值具有随机值; 提升归一化双对角矩阵; 确定提升的归一化双对角矩阵的每个子矩阵的循环列移位的偏移值; 以及确定对应于所述奇偶校验部分矩阵的列的奇偶校验符号。

公开(公告)号：US07458009B2

公开(公告)日：2008-11-25

申请号：US10563216

申请日：2004-10-14

申请人： Nam-Yul Yu ,  Min-Goo Kim

发明人： Nam-Yul Yu ,  Min-Goo Kim

IPC分类号： G06F11/00

CPC分类号： H03M13/1197 ,  H03M13/1114 ,  H03M13/1137 ,  H03M13/1162 ,  H03M13/118 ,  H03M13/1185 ,  H03M13/611

摘要： An apparatus and method for encoding low-density parity check (LDPC) codes. The method for generating a low-density parity check code formed of an information-part matrix and a parity-part matrix comprises the steps of converting the information-part matrix into an array code structure and assigning a degree sequence to each submatrix column; extending a dual-diagonal matrix corresponding to the parity-part matrix such that an offset value between diagonals has a random value; lifting the normalized dual-diagonal matrix; determining an offset value for cyclic column shift for each submatrix of the lifted normalized dual-diagonal matrix; and determining a parity symbol corresponding to a column of the parity-part matrix.

摘要翻译： 一种用于编码低密度奇偶校验（LDPC）码的装置和方法。 用于产生由信息部分矩阵和奇偶校验部分矩阵形成的低密度奇偶校验码的方法包括以下步骤：将信息部分矩阵转换为阵列码结构，并将度序列分配给每个子矩阵列; 扩展对应于奇偶校验部分矩阵的双对角矩阵，使得对角线之间的偏移值具有随机值; 提升归一化双对角矩阵; 确定提升的归一化双对角矩阵的每个子矩阵的循环列移位的偏移值; 以及确定对应于所述奇偶校验部分矩阵的列的奇偶校验符号。