公开(公告)号：US06777975B1

公开(公告)日：2004-08-17

申请号：US09451684

申请日：1999-11-30

申请人： Sanjay Dabral ,  Ming Zeng ,  Ramesh Senthinathan ,  Andrew M. Volk

发明人： Sanjay Dabral ,  Ming Zeng ,  Ramesh Senthinathan ,  Andrew M. Volk

IPC分类号： H03K1716

CPC分类号： G06F13/4086

摘要： A bus in which a transmission line is excited by a pMOSFET having a drain connected to the transmission line and having a source at a core voltage VCC, and in which the transmission line is terminated by a device connected to ground.

摘要翻译： 一种总线，其中传输线由具有连接到传输线并且具有核心电压VCC的源的pMOSFET激发，并且其中传输线由连接到地的设备终止。

公开(公告)号：US06601196B1

公开(公告)日：2003-07-29

申请号：US09608449

申请日：2000-06-29

申请人： Sanjay Dabral ,  Ramesh Senthinathan ,  Ming Zeng ,  Keith Self ,  Ernest Khaw ,  Chung-Wai Yue

发明人： Sanjay Dabral ,  Ramesh Senthinathan ,  Ming Zeng ,  Keith Self ,  Ernest Khaw ,  Chung-Wai Yue

IPC分类号： G06F1100

CPC分类号： G06F11/221

摘要： An apparatus and method for debugging a bus including interposing a device that monitors the data transferred between two devices on the bus such that the bus is split into two busses, with data being copied for transmission to a diagnostics device as the data is transferred between the two busses.

摘要翻译： 一种用于调试总线的装置和方法，包括插入监视总线上的两个设备之间传输的数据的设备，使得总线被分成两个总线，当数据被复制以传输到诊断设备时，数据在 两辆巴士。

公开(公告)号：US08286022B2

公开(公告)日：2012-10-09

申请号：US12352114

申请日：2009-01-12

申请人： Richard Fung ,  Ramesh Senthinathan ,  Nancy Chan

发明人： Richard Fung ,  Ramesh Senthinathan ,  Nancy Chan

IPC分类号： G06F1/12

CPC分类号： H03K5/151 ,  G06F1/10 ,  H04L25/0272 ,  H04L25/03878

摘要： A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with deterministic skew adjustment set during a receiver training period. Intrapair skew refers to the skew within a pair of differential signals, and is hence interchangeable with the term differential skew in the context of this document. During the receiver training period, a training data pattern is received, such as alternating ones and zeros (e.g., a D10.2 pattern as is known in the art), rather than an actual data payload. The differential serial communication receiver circuit includes a differential skew compensation circuit to compensate for intrapair skew. The differential skew compensation circuit receives a pair of complementary differential input signals including a noninverting input signal and an inverting input signal, and in response generates a skew compensated first differential output signal and a skew compensated second differential output signal. The differential skew compensation circuit compares the relative delay of the skew compensated first differential output signal and the skew compensated second differential output signal, and in response delays at least one of the noninverting input signal or the inverting input signal to reduce intrapair skew.

摘要翻译： 差分串行通信接收器电路自动补偿串行差分通信链路上接收到的差分信号之间的时间间隔偏移，并在接收机训练期间设置确定性偏移调整。 内部偏斜是指一对差分信号内的偏斜，因此可以与本文档上下文中的术语差分偏移互换。 在接收机训练期间，接收训练数据模式，例如交替的零和零（例如本领域已知的D10.2模式），而不是实际的数据有效载荷。 差分串行通信接收器电路包括差分偏移补偿电路，以补偿内部偏移。 差分偏移补偿电路接收包括非反相输入信号和反相输入信号的一对互补差分输入信号，并且响应于产生偏斜补偿的第一差分输出信号和偏斜补偿的第二差分输出信号。 差分偏移补偿电路比较偏斜补偿的第一差分输出信号和偏斜补偿的第二差分输出信号的相对延迟，并且响应延迟至少一个同相输入信号或反相输入信号，以减少行间偏斜。

公开(公告)号：US20070120583A1

公开(公告)日：2007-05-31

申请号：US11164622

申请日：2005-11-30

申请人： Shirley Lam ,  Nancy Chan ,  Mikhail Rodionov ,  Ramesh Senthinathan

发明人： Shirley Lam ,  Nancy Chan ,  Mikhail Rodionov ,  Ramesh Senthinathan

IPC分类号： H03L7/06

CPC分类号： H03L7/0802 ,  H03L7/0891 ,  H03L7/10

摘要： In a method and apparatus for using a clock generating circuit to minimize settling time after dynamic power supply voltage ramping, a clock signal may be generated using a clock generating circuit having, among other things, open feedback loop switch logic and a dynamic fast lock control signal generator. Whereupon, when in operation, the open feedback loop switch logic is responsive to a controlled change in power supply voltage condition such that a feedback loop of the clock generating circuit is opened during power supply voltage ramping (e.g., during transitions to or from battery conservation modes). In response to opening the feedback loop, the dynamic fast lock control signal generator selectively applies a stabilizing control signal to a variable clock signal generator (e.g., a voltage controlled oscillator) such that the generated clock signal can quickly lock onto the proper target frequency.

摘要翻译： 在使用时钟发生电路来最小化动态电源电压斜坡上的建立时间的方法和装置中，可以使用具有开放反馈回路开关逻辑和动态快速锁定控制的时钟产生电路来产生时钟信号 信号发生器。 于是，在运行时，开路反馈环路开关逻辑响应电源电压条件的受控变化，使得时钟发生电路的反馈回路在电源电压斜坡期间打开（例如，在转换到电池保护期间 模式）。 响应于打开反馈回路，动态快速锁定控制信号发生器选择性地将稳定控制信号施加到可变时钟信号发生器（例如，压控振荡器），使得所产生的时钟信号可以快速锁定到适当的目标频率上。

公开(公告)号：US20060244512A1

公开(公告)日：2006-11-02

申请号：US10908163

申请日：2005-04-29

申请人： Richard Fung ,  Ramesh Senthinathan

发明人： Richard Fung ,  Ramesh Senthinathan

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G09G2330/02

摘要： Methods and apparatus for matching voltages between two or more circuits within an integrated circuit is disclosed. The apparatus includes a comparator circuit, comparing supply voltages to first and second circuits. The comparator outputs a variable error voltage based on the comparison, the error voltage related to the difference in voltages. The error voltage is supplied to a variable current control circuit that variably sinks one of the supply voltages to a common potential in order to increase the IR drop in the circuit supplying voltage to one of the first and second circuits, thereby affording voltage adjustment in order to match the first and second circuits. A corresponding method is also disclosed.

摘要翻译： 公开了用于在集成电路内的两个或多个电路之间匹配电压的方法和装置。 该装置包括比较器电路，用于将电源电压与第一和第二电路进行比较。 比较器根据比较输出可变误差电压，即与电压差有关的误差电压。 误差电压被提供给可变电流控制电路，其将电源电压中的一个可变地吸收到公共电位，以便将电路中的IR降低增加到第一和第二电路中的一个，从而按顺序提供电压调整 以匹配第一和第二电路。 还公开了相应的方法。

公开(公告)号：US20060123177A1

公开(公告)日：2006-06-08

申请号：US11004201

申请日：2004-12-02

申请人： Nancy Chan ,  Ramesh Senthinathan

发明人： Nancy Chan ,  Ramesh Senthinathan

IPC分类号： G06F13/42

CPC分类号： H03L7/06 ,  H04L7/0008 ,  H04L25/0272 ,  H04L25/0276

摘要： A differential serial communication transmitter (i.e. PCI Express or other suitable type of transmitter) can be used to transport and interoperate transition minimized differential signaling. The differential serial communication transmitter control logic receives display configuration control data and in response configures at least one differential serial communication transmitter of a plurality of differential serial communication transmitters in an integrated circuit for communication with a display (i.e. visual digital display) employing transition minimized differential signaling. For example, the integrated circuit, such as a graphics processor, may include the plurality of differential serial communication transmitters for communication with devices, such as a northbridge circuit and a display within a computer system. The differential serial communication transmitter control logic may configure at least one of the plurality of differential serial communication transmitters for communication with the display via a differential serial communication display link (i.e. DVI or other suitable type of link). The plurality of differential serial communication transmitters may also be configured for communication with one or more other devices, such as with a bridge circuit such as a northbridge.

摘要翻译： 可以使用差分串行通信发射机（即PCI Express或其他合适类型的发射机）来传输和互操作转换最小化的差分信令。 差分串行通信发射机控制逻辑接收显示配置控制数据，并且作为响应，在集成电路中配置多个差分串行通信发射机的至少一个差分串行通信发射机，用于与使用转换最小化差分的显示器（即可视数字显示器）进行通信 信令。 例如，诸如图形处理器的集成电路可以包括用于与设备（例如北桥电路和计算机系统内的显示器）通信的多个差分串行通信发射器。 差分串行通信发射机控制逻辑可以配置多个差分串行通信发射机中的至少一个，用于经由差分串行通信显示链路（即，DVI或其他合适类型的链路）与显示器进行通信。 多个差分串行通信发射机还可以被配置为与一个或多个其他设备进行通信，例如用诸如北桥的桥接电路进行通信。

公开(公告)号：US08441310B2

公开(公告)日：2013-05-14

申请号：US13010595

申请日：2011-01-20

申请人： Ramesh Senthinathan ,  Hooman Moshar

发明人： Ramesh Senthinathan ,  Hooman Moshar

IPC分类号： G06F1/26 ,  G05F1/46

CPC分类号： G06F1/3296 ,  G06F1/3243 ,  Y02D10/152 ,  Y02D10/172 ,  Y10T307/858

摘要： According to an example embodiment, an apparatus for controlling a power supply voltage for an integrated circuit may be provided, which may include a plurality of different types of process region detection circuits, each process region detection circuit configured to identify a respective process region of a plurality of process regions. The apparatus may also include a voltage selection circuit configured to determine a highest voltage among the voltages associated with the identified process regions and to select a power supply voltage for the integrated circuit that is equal to the highest voltage, one or more functional test circuits configured to perform a functional test using the selected power supply voltage, and a voltage adjuster circuit configured to increase the selected power supply voltage if the functional test fails.

摘要翻译： 根据示例实施例，可以提供用于控制集成电路的电源电压的装置，其可以包括多个不同类型的处理区域检测电路，每个处理区域检测电路被配置为识别一个 多个处理区域。 该装置还可以包括电压选择电路，其被配置为确定与所识别的处理区域相关联的电压中的最高电压，并且选择等于最高电压的集成电路的电源电压，配置的一个或多个功能测试电路 使用所选择的电源电压来执行功能测试;以及电压调节器电路，其被配置为如果功能测试失败则增加所选择的电源电压。

公开(公告)号：US20110060847A1

公开(公告)日：2011-03-10

申请号：US12944501

申请日：2010-11-11

申请人： Nancy Chan ,  Ramesh Senthinathan

发明人： Nancy Chan ,  Ramesh Senthinathan

IPC分类号： G06F3/00 ,  G06F13/42

CPC分类号： H03L7/06 ,  H04L7/0008 ,  H04L25/0272 ,  H04L25/0276

摘要： A differential serial communication transmitter (i.e. PCI Express or other suitable type of transmitter) can be used to transport and interoperate transition minimized differential signaling. The differential serial communication transmitter control logic receives display configuration control data and in response configures at least one differential serial communication transmitter of a plurality of differential serial communication transmitters in an integrated circuit for communication with a display (i.e. visual digital display) employing transition minimized differential signaling. For example, the integrated circuit, such as a graphics processor, may include the plurality of differential serial communication transmitters for communication with devices, such as a northbridge circuit and a display within a computer system. The differential serial communication transmitter control logic may configure at least one of the plurality of differential serial communication transmitters for communication with the display via a differential serial communication display link (i.e. DVI or other suitable type of link). The plurality of differential serial communication transmitters may also be configured for communication with one or more other devices, such as with a bridge circuit such as a northbridge.

公开(公告)号：US20090121761A1

公开(公告)日：2009-05-14

申请号：US12352114

申请日：2009-01-12

申请人： Richard Fung ,  Ramesh Senthinathan ,  Nancy Chan

发明人： Richard Fung ,  Ramesh Senthinathan ,  Nancy Chan

IPC分类号： H03L7/00

CPC分类号： H03K5/151 ,  G06F1/10 ,  H04L25/0272 ,  H04L25/03878

摘要： A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with deterministic skew adjustment set during a receiver training period. Intrapair skew refers to the skew within a pair of differential signals, and is hence interchangeable with the term differential skew in the context of this document. During the receiver training period, a training data pattern is received, such as alternating ones and zeros (e.g., a D10.2 pattern as is known in the art), rather than an actual data payload. The differential serial communication receiver circuit includes a differential skew compensation circuit to compensate for intrapair skew. The differential skew compensation circuit receives a pair of complementary differential input signals including a noninverting input signal and an inverting input signal, and in response generates a skew compensated first differential output signal and a skew compensated second differential output signal. The differential skew compensation circuit compares the relative delay of the skew compensated first differential output signal and the skew compensated second differential output signal, and in response delays at least one of the noninverting input signal or the inverting input signal to reduce intrapair skew.

摘要翻译： 差分串行通信接收器电路自动补偿串行差分通信链路上接收到的差分信号之间的时间间隔偏移，并在接收机训练期间设置确定性偏移调整。 内部偏斜是指一对差分信号内的偏斜，因此可以与本文档上下文中的术语差分偏移互换。 在接收机训练期间，接收训练数据模式，例如交替的零和零（例如本领域已知的D10.2模式），而不是实际的数据有效载荷。 差分串行通信接收器电路包括差分偏移补偿电路，以补偿内部偏移。 差分偏移补偿电路接收包括非反相输入信号和反相输入信号的一对互补差分输入信号，并且响应于产生偏斜补偿的第一差分输出信号和偏斜补偿的第二差分输出信号。 差分偏移补偿电路比较偏斜补偿的第一差分输出信号和偏斜补偿的第二差分输出信号的相对延迟，并且响应延迟至少一个同相输入信号或反相输入信号，以减少行间偏斜。

公开(公告)号：US20090115457A1

公开(公告)日：2009-05-07

申请号：US12352916

申请日：2009-01-13

申请人： Junho Cho ,  Nancy Chan ,  Ramesh Senthinathan ,  Stephen Yue ,  Richard W. Fung

发明人： Junho Cho ,  Nancy Chan ,  Ramesh Senthinathan ,  Stephen Yue ,  Richard W. Fung

IPC分类号： H03K19/20

CPC分类号： H03K17/302 ,  H03K17/04106

摘要： The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.

摘要翻译： 本公开涉及一种差分信号电路，其包括具有至少一个输出和一个输入的差分信号电路，其可以在使用单个低电压电源时在多种操作模式下操作。 两个或更多个开关被包括并且被配置为根据差分信号电路的操作模式来选择性地将电源电压耦合到输出。 电路还包括可操作地耦合到至少一个开关和差分信号电路的输出的开关控制偏置电路。 开关控制偏置电路提供开关控制偏置电压，以基于输出的电压电平来控制开关的状态。 此外，体积偏置电路被包括并且可操作地耦合到开关。 体积偏置电路基于输出的电压电平选择性地向开关提供体积偏置电压。