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    Hardware-based rate control for bursty traffic
    1.
    发明授权
    Hardware-based rate control for bursty traffic 有权
    突发性流量的基于硬件的速率控制

    公开(公告)号：US07652988B2

    公开(公告)日：2010-01-26

    申请号：US10446419

    申请日：2003-05-28

    申请人： Sanjay Jain ,  Deepak Aatresh ,  Daniel M. Hegglin

    发明人： Sanjay Jain ,  Deepak Aatresh ,  Daniel M. Hegglin

    IPC分类号： H04L12/26

    CPC分类号： H04L47/10

    摘要： A hardware-based rate control engine is designed to allow credits to be accumulated over multiple time-slices up to a maximum credit limit. The rate control engine is also allowed to dispatch packets up to a maximum drain rate during each time-slice as long as sufficient credits are available. Allowing credits to accumulate over multiple time slices allows unused bandwidth to be saved during times of little or no traffic and used when the subsequent traffic bursts arrive. Additionally, limiting the maximum drain rate puts a cap on how fast the saved bandwidth can be consumed by subsequent traffic bursts. The rate control settings can be adapted in response to a characteristic, or characteristics, of the traffic flow. For example, one group of settings of a traffic flow can be used for bursty traffic, while a different group of settings can be used for smooth traffic.

    摘要翻译： 基于硬件的速率控制引擎被设计为允许在多个时间片上积累信用以达到最大信用限额。 只要有足够的信用额度，速率控制引擎也可以在每个时间片段内调度数据包，达到最大排放速率。 允许信用累积多个时间片允许在很少或没有流量的时间内保存未使用的带宽，并且在随后的业务突发到达时使用。 另外，限制最大漏极率可以说明随后的业务脉冲串可以节省多长时间的带宽。 速率控制设置可以响应于业务流的特性或特性进行调整。 例如，流量的一组设置可以用于突发流量，而不同的设置组可用于平滑流量。

    REDUCTION OF ENDOTOXIN IN POLYSIALIC ACIDS
    2.
    发明申请
    REDUCTION OF ENDOTOXIN IN POLYSIALIC ACIDS 审中-公开
    减少多糖中的内毒素

    公开(公告)号：US20110159130A1

    公开(公告)日：2011-06-30

    申请号：US12528763

    申请日：2008-02-28

    申请人： Sanjay Jain ,  Peter Laing ,  Gregory Gregoriadis

    发明人： Sanjay Jain ,  Peter Laing ,  Gregory Gregoriadis

    IPC分类号： A61K35/74 ,  C07K14/00 ,  C12P21/06

    CPC分类号： C08B37/0006 ,  B01D15/363 ,  C08B37/0003

    摘要： The present invention relates to process for reducing the endotoxin content of a sample of fermentation broth containing polysialic acid and endotoxin comprising the sequential steps: (i) adding to the sample a base having a pKa of at least 12 to form a basic solution having a pH of at least 12, incubating the solution for a pre-determined time at a pre-determined temperature; and (ii) recovery of PSA, suitably by (iii) passing the sample through an anion-exchange column whereby polysialic acid is absorbed on the ion exchange resin; (iv) washing the column with one washing buffer, whereby polysialic acid remains absorbed on the ion exchange resin; and (v) eluting the polysialic acid from the column using an elution buffer to provide a product solution of polysialic acid having reduced endotoxin content.

    摘要翻译： 本发明涉及降低含有唾液酸和内毒素的发酵肉汤样品的内毒素含量的方法，其包括以下顺序步骤：（i）向样品中加入pKa至少为12的碱，以形成具有 pH至少为12，在预定温度下将溶液温育预定时间; 和（ii）PSA的回收，适当地通过（iii）使样品通过阴离子交换柱，由此唾液酸被吸收在离子交换树脂上; （iv）用一个洗涤缓冲液洗涤该柱，由此聚唾液酸保持吸收在离子交换树脂上; 和（v）使用洗​​脱缓冲液从柱洗脱聚唾液酸以提供具有降低的内毒素含量的聚唾液酸的产物溶液。

    Methods and apparatus to manage shadow copy providers
    3.
    发明申请
    Methods and apparatus to manage shadow copy providers 有权
    管理影子拷贝提供者的方法和设备

    公开(公告)号：US20070179980A1

    公开(公告)日：2007-08-02

    申请号：US11343012

    申请日：2006-01-30

    申请人： Wei Liu ,  Sanjay Jain

    发明人： Wei Liu ,  Sanjay Jain

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30067

    摘要： A data storage management system includes a virtual provider for interacting with a coordinator to receive shadow copy requests from a requestor and for interfacing with a plurality of providers that support various logical units on which data volumes can be stored. The virtual provider appears to the coordinator as a provider and can generate a shadow copy of a first one of the data volumes that spans multiple ones of the logical units, which are supported by different ones of the plurality of providers.

    摘要翻译： 数据存储管理系统包括用于与协调器进行交互以接收来自请求者的卷影复制请求的虚拟提供者，以及用于与支持能够存储数据卷的各种逻辑单元的多个提供者进行接口。 虚拟提供商作为提供者向协调器显示，并且可以生成跨越多个逻辑单元的第一个数据卷的第一个卷影副本，这些多个逻辑单元由多个提供者中的不同的提供者支持。

    Monitoring and controlling work progress
    4.
    发明申请
    Monitoring and controlling work progress 审中-公开
    监测和控制工作进展

    公开(公告)号：US20050240561A1

    公开(公告)日：2005-10-27

    申请号：US11113565

    申请日：2005-04-25

    申请人： Sanjay Jain ,  Anthony Amato

    发明人： Sanjay Jain ,  Anthony Amato

    IPC分类号： G06F7/00 ,  G06Q10/00

    CPC分类号： G06Q10/06

    摘要： The invention relates to products for, and methods of, monitoring and controlling work progress, and improving work productivity and work management, for example in highly variable and/or unpredictable work environments, and to products for, and methods of, interactive data processing particularly adapted for systems comprising a handheld mobile component

    摘要翻译： 本发明涉及例如在高度可变和/或不可预测的工作环境中的工作进展的产品和监测和控制方法，以及提高工作效率和工作管理，以及交互式数据处理的产品和方法，特别是 适用于包括手持移动组件的系统

    Power management for low power processors through the use of auto clock-throttling
    7.
    发明授权
    Power management for low power processors through the use of auto clock-throttling 失效
    通过使用自动时钟调节功能管理低功耗处理器

    公开(公告)号：US5586332A

    公开(公告)日：1996-12-17

    申请号：US036343

    申请日：1993-03-24

    申请人： Sanjay Jain ,  Deepak J. Aatresh

    发明人： Sanjay Jain ,  Deepak J. Aatresh

    IPC分类号： G06F1/32

    CPC分类号： G06F9/3885 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  G06F9/30083 ,  G06F9/3869 ,  Y02B60/1221 ,  Y02B60/1282 ,  Y02B60/32

    摘要： A clock throttling mechanism turns off certain processor components to minimize power consumption. The processor detects the issuance of certain bus cycles or the execution of certain instructions which typically cause the processor to be idle for a period of time. Control circuitry detects the existence of the instruction and/or bus cycle and shuts down the clock driving certain processor components during that idle period. The control circuitry then detects the occurrence or upcoming occurrence of an event to which the processor responds and becomes active. At detection of this event, the clock signal input to these components is then restarted such that the processor can continue normal execution.

    摘要翻译： 时钟调节机制关闭某些处理器组件以最小化功耗。 处理器检测某些总线周期的发布或某些指令的执行，这些指令通常会导致处理器空闲一段时间。 控制电路检测指令和/或总线周期的存在，并在该空闲期间关闭驱动某些处理器组件的时钟。 然后，控制电路检测处理器响应并发生事件的发生或即将发生。 在检测到该事件时，输入到这些组件的时钟信号然后重新启动，使得处理器可以继续正常执行。

    Method and apparatus for reduced latency in hold bus cycles
    8.
    发明授权
    Method and apparatus for reduced latency in hold bus cycles 失效
    在保持总线周期中减少延迟的方法和装置

    公开(公告)号：US5398244A

    公开(公告)日：1995-03-14

    申请号：US92488

    申请日：1993-07-16

    申请人： Gregory S. Mathews ,  Deepak J. Aatresh ,  Sanjay Jain

    发明人： Gregory S. Mathews ,  Deepak J. Aatresh ,  Sanjay Jain

    IPC分类号： G06F13/30 ,  G06F13/364 ,  H04J3/00

    CPC分类号： G06F13/364 ,  G06F13/30

    摘要： An innovative protocol and system for implementing the same enables quick release of the bus by the master device, such as a CPU, to permit slave devices access to the bus. In one embodiment, the arbiter can select between the original hold protocol and quick hold protocol according to predetermined criteria which indicates that a low latency response is requested. Upon assertion of a QHOLD signal, the CPU issues a burst last signal to prematurely terminate outstanding burst transactions on the bus in a manner transparent to the slave devices. Once the outstanding bus cycles are complete, the CPU performs an internal backoff to immediately release the bus for access by the slave device requesting access. Any pending burst cycles which were terminated prematurely by the QHOLD signal, are subsequently restarted for the data not transacted by the CPU after the slave device completes access to the bus. The internal backoff mechanism is similarly transparent to the slave devices and does not cause a backoff signal to be issued to the peripherals or devices coupled to the bus. Thus, the addition of a quick hold protocol is added without significant modification of the slave devices' bus interface.

    摘要翻译： 用于实现该协议和系统的创新协议和系统能够通过主设备（例如CPU）快速释放总线，以允许从设备访问总线。 在一个实施例中，仲裁器可以根据预定标准在原始保持协议和快速保持协议之间进行选择，这些标准指示请求低延迟响应。 在断言QHOLD信号时，CPU以对从属设备透明的方式发出突发上一个信号以提前终止总线上的突发事件。 一旦未完成的总线周期完成，CPU将执行内部退避，以立即释放总线以供从机设备请求访问。 随后，在从站设备完成对总线的访问之后，由QHOLD信号提前终止的任何未决突发周期随后重新启动，以便CPU不处理数据。 内部退避机制对于从属设备类似地是透明的，并且不会导致向连接到总线的外围设备或设备发出退避信号。 因此，添加快速保持协议，而不显着修改从设备的总线接口。