公开(公告)号：US20050238010A1

公开(公告)日：2005-10-27

申请号：US10832796

申请日：2004-04-26

申请人： Rina Panigrahy ,  Jackie Liu ,  Daniel Ng ,  Sanjay Jain ,  Nagaraj Bagepalli ,  Abhijit Patra

发明人： Rina Panigrahy ,  Jackie Liu ,  Daniel Ng ,  Sanjay Jain ,  Nagaraj Bagepalli ,  Abhijit Patra

IPC分类号： H04L12/56 ,  H04L29/06

CPC分类号： H04L63/0254 ,  H04L63/1408 ,  H04L69/22

摘要： The present invention provides a packet processing device and method. A parsing processor provides instruction-driven content inspection of network packets at 10-Gbps and above with a parsing engine that executes parsing instructions. A flow state unit maintains statefulness of packet flows to allow content inspection across several related network packets. A state-graph unit traces state-graph nodes to keyword indications and/or parsing instructions. The parsing instructions can be derived from a high-level application to emulate user-friendly parsing logic. The parsing processor sends parsed packets to a network processor unit for further processing.

摘要翻译： 本发明提供一种分组处理装置和方法。 解析处理器使用执行解析指令的解析引擎，以10Gbps及以上的网络分组提供指令驱动的内容检查。 流状态单元保持分组流的状态，以允许跨多个相关网络分组的内容检查。 状态图单元将状态图节点跟踪到关键字指示和/或解析指令。 解析指令可以从高级应用程序导出，以模拟用户友好的解析逻辑。 解析处理器将解析的分组发送到网络处理器单元用于进一步处理。

公开(公告)号：US20050238012A1

公开(公告)日：2005-10-27

申请号：US10927290

申请日：2004-08-25

申请人： Rina Panigrahy ,  Jackie Liu ,  Daniel Ng ,  Sanjay Jain ,  Nagaraj Bagepalli ,  Abhijit Patra

发明人： Rina Panigrahy ,  Jackie Liu ,  Daniel Ng ,  Sanjay Jain ,  Nagaraj Bagepalli ,  Abhijit Patra

IPC分类号： H04L12/56 ,  H04L29/06

CPC分类号： H04L63/0254 ,  H04L63/1408 ,  H04L69/22

摘要： The present invention provides a packet processing device and method. A parsing processor provides instruction-driven content inspection of network packets at 10-Gbps and above with a parsing engine that executes parsing instructions. A flow state unit maintains statefulness of packet flows to allow content inspection across several related network packets. A state-graph unit traces state-graph nodes to keyword indications and/or parsing instructions. The parsing instructions can be derived from a high-level application to emulate user-friendly parsing logic. The parsing processor sends parsed packets to a network processor unit for further processing.

公开(公告)号：US20160247899A1

公开(公告)日：2016-08-25

申请号：US14629229

申请日：2015-02-23

申请人： Anup Bhalla ,  Daniel Ng ,  Tiesheng Li ,  Sik K. Lui

发明人： Anup Bhalla ,  Daniel Ng ,  Tiesheng Li ,  Sik K. Lui

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/3213 ,  H01L29/08

CPC分类号： H01L29/66712 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7827

摘要： This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

摘要翻译： 本发明公开了一种支撑在半导体上的新开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的所述半导体的第二表面附近的源极区域。 开关装置还包括设置在第二表面顶部的用于控制源极到漏极电流的绝缘栅电极。 开关装置还包括插入到绝缘栅电极中的源电极，用于基本上防止栅电极和绝缘栅电极下方的外延区之间的电场的耦合。 源电极进一步覆盖并延伸在绝缘栅上，以覆盖半导体的第二表面上的区域以接触源区。 半导体衬底还包括设置在漏极区以上且具有与漏极区不同的掺杂浓度的外延层。 绝缘栅电极还包括用于使栅电极与源电极绝缘的绝缘层，其中绝缘层的厚度取决于垂直功率器件的Vgsmax等级。

公开(公告)号：US08802530B2

公开(公告)日：2014-08-12

申请号：US13490138

申请日：2012-06-06

申请人： Xiaobin Wang ,  Anup Bhalla ,  Daniel Ng

发明人： Xiaobin Wang ,  Anup Bhalla ,  Daniel Ng

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/42

CPC分类号： H01L29/7813 ,  H01L21/42 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66734

摘要： A semiconductor power device includes a thick bottom insulator formed in a lower portion of a trench in a semiconductor epitaxial region. An electrically conductive gate electrode is formed in the trench above the bottom insulator. The gate electrode is electrically insulated from the epitaxial region by the bottom insulator and a gate insulator. Charge is deliberately induced in the thick bottom insulator proximate an interface between the bottom insulator and the epitaxial semiconductor region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 半导体功率器件包括形成在半导体外延区域中的沟槽的下部的厚的底部绝缘体。 在底部绝缘体上方的沟槽中形成导电栅电极。 栅极电极通过底部绝缘体和栅极绝缘体与外延区域电绝缘。 在底部绝缘体和外延半导体区域之间的界面附近的厚底层绝缘体中有意地引起电荷。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20140175540A1

公开(公告)日：2014-06-26

申请号：US13724093

申请日：2012-12-21

申请人： Madhur Bobde ,  Hamza Yilmaz ,  Sik Lui ,  Daniel Ng

发明人： Madhur Bobde ,  Hamza Yilmaz ,  Sik Lui ,  Daniel Ng

IPC分类号： H01L27/04 ,  H01L21/82

CPC分类号： H01L29/7813 ,  H01L21/2257 ,  H01L27/0251 ,  H01L27/04 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7808 ,  H01L29/7811

摘要： Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开的方面描述了具有自对准源触点的高密度沟槽基功率MOSFET和用于制造这种器件的方法。 源触点与间隔物自对准，并且有源器件可以具有两步栅极氧化物。 下部可以具有比栅极氧化物的上部的厚度大的厚度。 MOSFET也可以在衬底的下部包括可消除的屏蔽。 可消除的屏蔽可以被配置成使得在高排水偏压期间，屏蔽件基本上消耗掉。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US08692322B2

公开(公告)日：2014-04-08

申请号：US13539330

申请日：2012-08-26

申请人： Ji Pan ,  Daniel Ng ,  Anup Bhalla ,  Xiaobin Wang

发明人： Ji Pan ,  Daniel Ng ,  Anup Bhalla ,  Xiaobin Wang

IPC分类号： H01L27/088

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

摘要翻译： 半导体功率器件包括多个功率晶体管单元，每个功率晶体管单元各自具有设置在栅极沟槽中的沟槽栅极，其中沟槽栅极包括设置在栅极沟槽的底部部分中的屏蔽底部电极，该顶部电极与设置在顶部的顶部栅电极电绝缘 栅极沟槽的部分通过电极间绝缘层。 晶体管单元中的至少一个包括用作与半导体功率器件的源电极电连接的源极连接屏蔽底部电极的屏蔽底部电极，以及具有用作栅极连接的屏蔽底部电极的至少一个晶体管单元， 连接屏蔽底电极，电连接到半导体功率器件的栅极金属。

公开(公告)号：US20130200451A1

公开(公告)日：2013-08-08

申请号：US13364948

申请日：2012-02-02

申请人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

发明人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0626 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.

摘要翻译： 半导体功率器件可以包括在重掺杂层上形成的轻掺杂层。 在轻掺杂层中形成一个或多个器件。 每个器件可以包括主体区域，源极区域和形成在轻掺杂区域中的对应沟槽中的一个或多个栅电极。 每个沟槽具有第一维度的深度，第二维度中的宽度和第三维度中的长度。 体区与轻掺杂层和重掺杂层具有相反的导电类型。 源区域靠近上表面形成。 在靠近一个或多个沟槽的第三维度的一个或多个位置处形成一个或多个深触点。 触点在第一方向上从上表面延伸到轻掺杂层中并与源区电接触。

公开(公告)号：US20130049100A1

公开(公告)日：2013-02-28

申请号：US13216122

申请日：2011-08-23

申请人： Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Jun Lu

发明人： Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Jun Lu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L21/30604 ,  H01L21/30608 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/83 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0657 ,  H01L29/0886 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/8309 ,  H01L2224/83141 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson (drain-source on resistance) of power MOSFETs, and a power MOSFET device made by the method. By forming one or more bottom grooves at the bottom of Si substrate, the on resistance of the power MOSFET device attributed to the substrate is effectively reduced. A matching lead frame base complementary to the substrate with bottom grooves further improves the package of the power MOSFET device.

摘要翻译： 本发明涉及功率半导体器件及其制备方法。 特别地，本发明旨在提供一种降低功率MOSFET的Rdson（漏源电阻）的基板贡献的方法以及通过该方法制造的功率MOSFET器件。 通过在Si衬底的底部形成一个或多个底部沟槽，有效地降低归因于衬底的功率MOSFET器件的导通电阻。 与具有底槽的衬底互补的匹配引线框架底座进一步改善了功率MOSFET器件的封装。

公开(公告)号：US20130043527A1

公开(公告)日：2013-02-21

申请号：US13212940

申请日：2011-08-18

申请人： SIK LUI ,  Yi Su ,  Daniel Ng ,  Daniel Calafut ,  Anup Bhalla

发明人： SIK LUI ,  Yi Su ,  Daniel Ng ,  Daniel Calafut ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L23/647 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L2224/0603 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A shielded gate trench field effect transistor can be formed on a substrate having an epitaxial layer on the substrate and a body layer on the epitaxial layer. A trench formed in the body layer and epitaxial layer is lined with a dielectric layer. A shield electrode is formed within a lower portion of the trench. The shield electrode is insulated by the dielectric layer. A gate electrode is formed in the trench above the shield electrode and insulated from the shield electrode by an additional dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the one or more source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element can be electrically connected between the shield electrode pad and the source lead in the package.

摘要翻译： 可以在衬底上具有外延层的衬底上形成屏蔽栅沟槽场效应晶体管，并在外延层上形成体层。 形成在体层和外延层中的沟槽衬有介电层。 屏蔽电极形成在沟槽的下部内。 屏蔽电极由电介质层绝缘。 栅极电极形成在屏蔽电极上方的沟槽中，并通过附加的介电层与屏蔽电极绝缘。 形成在体层内的一个或多个源极区域与沟槽的侧壁相邻。 形成在主体层上方的源极焊盘与一个或多个源极区域电连接并与栅电极和屏蔽电极绝缘。 源极焊盘提供与源极区域的外部接触。 栅极焊盘提供与栅电极的外部接触。 屏蔽电极焊盘提供与屏蔽电极的外部接触。 电阻元件可以电连接在封装中的屏蔽电极焊盘和源极引线之间。

公开(公告)号：US20130015550A1

公开(公告)日：2013-01-17

申请号：US13184488

申请日：2011-07-15

申请人： Anup Bhalla ,  Ji Pan ,  Daniel Ng

发明人： Anup Bhalla ,  Ji Pan ,  Daniel Ng

IPC分类号： H01L29/872 ,  H01L21/283

CPC分类号： H01L29/872 ,  H01L24/05 ,  H01L29/0619 ,  H01L29/417 ,  H01L2924/01029 ,  H01L2924/12032 ,  H01L2924/00

摘要： A semiconductor junction barrier Schottky (JBS-SKY) diode with enforced upper contact structure (EUCS) is disclosed. Referencing an X-Y-Z coordinate, the JBS-SKY diode has semiconductor substrate (SCST) parallel to X-Y plane. Active device zone (ACDZ) atop SCST and having a JBS-SKY diode with Z-direction current flow. Peripheral guarding zone (PRGZ) atop SCST and surrounding the ACDZ. The ACDZ has active lower semiconductor structure (ALSS) and enforced active upper contact structure (EUCS) atop ALSS. The EUC has top contact metal (TPCM) extending downwards and in electrical conduction with bottom of EUCS; and embedded bottom supporting structure (EBSS) inside TPCM and made of a hard material, the EBSS extending downwards till bottom of the EUCS. Upon encountering bonding force onto TPCM during packaging of the JBS-SKY diode, the EBSS enforces the EUCS against an otherwise potential micro cracking of the TPCM degrading the leakage current of the JBS-SKY diode.

摘要翻译： 公开了一种具有强制上接触结构（EUCS）的半导体结屏障肖特基（JBS-SKY）二极管。 参考X-Y-Z坐标，JBS-SKY二极管具有与X-Y平面平行的半导体衬底（SCST）。 有源器件区（ACDZ）位于SCST上方，并具有Z方向电流流动的JBS-SKY二极管。 外围防护区（PRGZ）在SCST顶部并围绕ACDZ。 ACDZ在ALSS顶部具有活性较低的半导体结构（ALSS）和强制性的上接触结构（EUCS）。 EUC具有向下延伸并与EUCS底部导电的顶部接触金属（TPCM）; 并在TPCM内部嵌入底部支撑结构（EBSS），由硬质材料制成，EBSS向下延伸至EUCS底部。 在JBS-SKY二极管封装期间遇到TPCM上的结合力时，EBSS强制EUCS抵抗TPCM的另外潜在的微裂纹，降低JBS-SKY二极管的漏电流。