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1.发明申请PROCESSOR POWER CONSUMPTION CONTROL AND VOLTAGE DROP VIA MICRO-ARCHITECTURAL BANDWIDTH THROTTLING 审中-公开处理器消耗电力控制和电压降通过微结构带宽折射公开(公告)号：US20120210105A1
公开(公告)日：2012-08-16
申请号：US13212042
申请日：2011-08-17
IPC分类号： G06F9/30
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.
摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法包括向处理器提供第一电压。 该方法还包括允许处理器在第一电压下在增强的处理器停止状态下起作用。 第一电压是低于用于增强的处理器停止状态的最低兼容电压的电压。 该方法允许处理器在通过在处理器中执行的指令的最大吞吐速率从第一电压处的增强型处理器停止状态唤醒时执行指令。
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2.发明授权公开(公告)号：US08028181B2
公开(公告)日：2011-09-27
申请号：US12284303
申请日：2008-09-19
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.
摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法包括向处理器提供第一电压。 该方法还包括允许处理器在第一电压下在增强的处理器停止状态下起作用。 第一电压是低于用于增强的处理器停止状态的最低兼容电压的电压。 该方法允许处理器在通过在处理器中执行的指令的最大吞吐速率从第一电压处的增强型处理器停止状态唤醒时执行指令。
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3.发明申请公开(公告)号：US20100077232A1
公开(公告)日：2010-03-25
申请号：US12284303
申请日：2008-09-19
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.
摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法包括向处理器提供第一电压。 该方法还包括允许处理器在第一电压下在增强的处理器停止状态下起作用。 第一电压是低于用于增强的处理器停止状态的最低兼容电压的电压。 该方法允许处理器在通过在处理器中执行的指令的最大吞吐速率从第一电压处的增强型处理器停止状态唤醒时执行指令。
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4.发明授权Selective interrupt delivery to multiple processors having independent operating systems 失效选择性中断传递到具有独立操作系统的多个处理器公开(公告)号：US06976099B2
公开(公告)日：2005-12-13
申请号：US10865220
申请日：2004-06-09
CPC分类号： G06F9/4812 , G06F13/24 , Y02D10/14 , Y02D10/24
摘要： A method of and apparatus for selective delivery of an interrupt to one of multiple processors having independent operating systems is described. The interrupts are generated from various platform devices in the computer system. Depending on the mode of operation of the system, a controller is configured to deliver interrupts to a co-processor when the host processor is off, without turning on the host processor. The interrupt may be delivered to the correct processor using wither a bus-based message or a dedicated interrupt line.
摘要翻译： 描述了一种用于向具有独立操作系统的多个处理器之一选择性地传递中断的方法和装置。 中断由计算机系统中的各种平台设备生成。 根据系统的操作模式，控制器被配置为在主处理器关闭时向协处理器传送中断，而不打开主机处理器。 可以使用基于总线的消息或专用中断线将中断传送到正确的处理器。
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5.发明授权Method and apparatus for mapping address space of integrated programmable devices within host system memory 有权用于映射主机系统存储器内集成可编程设备的地址空间的方法和装置公开(公告)号：US06748512B2
公开(公告)日：2004-06-08
申请号：US09733875
申请日：2000-12-08
IPC分类号： G06F1208
CPC分类号： G06F12/0284 , G06F12/0835
摘要： A Method and Apparatus for Mapping Address Space of Integrated Programmable Devices within Host System Memory is described herein.
摘要翻译： 本文描述了用于映射主机系统存储器内的集成可编程设备的地址空间的方法和装置。
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6.发明授权Selective interrupt delivery to multiple processors having independent operating systems 有权选择性中断传递到具有独立操作系统的多个处理器公开(公告)号：US06772241B1
公开(公告)日：2004-08-03
申请号：US09676463
申请日：2000-09-29
IPC分类号： G06F500
CPC分类号： G06F9/4812 , G06F13/24 , Y02D10/14 , Y02D10/24
摘要： A method of and apparatus for selective delivery of an interrupt to one of multiple processors having independent operating systems is described. The interrupts are generated from various platform devices in the computer system. Depending on the mode of operation of the system, a controller is configured to deliver interrupts to a co-processor when the host processor is off, without turning on the host processor. The interrupt may be delivered to the correct processor using either a bus-based message or a dedicated interrupt line.
摘要翻译： 描述了一种用于向具有独立操作系统的多个处理器之一选择性地传递中断的方法和装置。 中断由计算机系统中的各种平台设备生成。 根据系统的操作模式，控制器被配置为在主处理器关闭时向协处理器传送中断，而不打开主机处理器。 可以使用基于总线的消息或专用中断线将中断传送到正确的处理器。
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