公开(公告)号：US07231497B2

公开(公告)日：2007-06-12

申请号：US10867884

申请日：2004-06-15

申请人： Sanjeev N. Trika ,  John I. Garney ,  Michael K. Eschmann

发明人： Sanjeev N. Trika ,  John I. Garney ,  Michael K. Eschmann

IPC分类号： G06F12/00

CPC分类号： G06F12/0804 ,  G06F12/0866

摘要： In one embodiment, the present invention includes a method for writing data to a disk if inserting the data into a cache, such as a disk cache associated with the disk, would cause a threshold of dirty data in the cache to be met or exceeded. Further, in certain embodiments, the cache may store data according to a first cache policy and a second cache policy. A determination of whether to store data according to the first or second policies may be dependent upon an amount of dirty data in the cache, in certain embodiments. In certain embodiments, the cache may include at least one portion reserved for clean data.

摘要翻译： 在一个实施例中，本发明包括如果将数据插入诸如与该磁盘相关联的磁盘高速缓存的高速缓存中时将数据写入到磁盘的方法，将导致满足或超过高速缓存中的脏数据的阈值。 此外，在某些实施例中，高速缓存可以根据第一高速缓存策略和第二高速缓存策略来存储数据。 在某些实施例中，根据第一或第二策略是否存储数据的确定可以取决于高速缓存中的脏数据量。 在某些实施例中，高速缓存可以包括为干净数据保留的至少一个部分。

公开(公告)号：US06630931B1

公开(公告)日：2003-10-07

申请号：US08935314

申请日：1997-09-22

申请人： Sanjeev N. Trika ,  John I. Garney

发明人： Sanjeev N. Trika ,  John I. Garney

IPC分类号： G06T1500

CPC分类号： H04N13/275

摘要： A method and apparatus for generating stereoscopic displays in a computer system. Each frame in a sequence of frames includes a left image and a right image, and each image includes a plurality of pixels. Depth information for objects depicted in the display is stored in a z buffer. Either the left image or the right image is computed as an approximation of the other using the depth information stored in the z buffer. The approximated image is alternated between the left and the right image on a frame-by-frame basis, so that the left and right image are each approximated every other frame. Pixels which are not filled in the approximated image are assigned values based on the corresponding pixels in the same (non-approximated) image from the preceding frame.

摘要翻译： 一种用于在计算机系统中产生立体显示的方法和装置。 帧序列中的每帧包括左图像和右图像，并且每个图像包括多个像素。 在显示器中描绘的对象的深度信息存储在z缓冲器中。 使用存储在z缓冲器中的深度信息来计算左图像或右图像作为另一图像的近似值。 近似图像在逐帧的基础上在左图像和右图像之间交替，使得左和右图像每个其他帧各自近似。 未填充在近似图像中的像素基于来自前一帧的相同（非近似）图像中的相应像素分配值。

公开(公告)号：US08479208B2

公开(公告)日：2013-07-02

申请号：US11694276

申请日：2007-03-30

申请人： Stephen J. Tolopka ,  David A. Koufaty ,  John I. Garney ,  Yasser Rasheed ,  Ulhas Warrier ,  Matthew Hoekstra

发明人： Stephen J. Tolopka ,  David A. Koufaty ,  John I. Garney ,  Yasser Rasheed ,  Ulhas Warrier ,  Matthew Hoekstra

IPC分类号： G06F9/50

CPC分类号： G06F9/5077 ,  G06F8/65 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/1491 ,  G06F21/74

摘要： Embodiments of apparatuses, methods for partitioning systems, and partitionable and partitioned systems are disclosed. In one embodiment, a system includes processors and a partition manager. The partition manager is to allocate a subset of the processors to a first partition and another subset of the processors to a second partition. The first partition is to execute first operating system level software and the second partition is to execute second operating system level software. The first operating system level software is to manage the processors in the first partition as resources individually accessible to the first operating system level software, and the second operating system level software is to manage the processors in the second partition as resources individually accessible to the second operating system level software. The partition manager is also to present the second partition, including the second operating system level software, to the first operating system level software as platform level functionality embedded in the system.

摘要翻译： 公开了装置的实施例，分区系统的方法以及可分割和分区的系统。 在一个实施例中，系统包括处理器和分区管理器。 分区管理器将处理器的子集分配给第一分区，另一个处理器子集分配给第二分区。 第一个分区是执行第一个操作系统级软件，第二个分区是执行第二个操作系统级软件。 第一操作系统级软件是将第一分区中的处理器作为第一操作系统级软件单独访问的资源进行管理，而第二操作系统级软件则将第二分区中的处理器作为第二分区可访问的资源进行管理 操作系统级软件。 分区管理器还将第二分区（包括第二操作系统级软件）呈现给第一操作系统级软件，作为嵌入系统中的平台级功能。

公开(公告)号：US08146089B2

公开(公告)日：2012-03-27

申请号：US11452756

申请日：2006-06-14

申请人： John I. Garney

发明人： John I. Garney

IPC分类号： G06F9/46

CPC分类号： G06F9/5077

摘要： In one embodiment, the present invention includes a method for allocating at least one dedicated core and at least one shareable core to a first partition of a system, where the cores are owned by the first partition. During operation, the shareable core(s) may be made dynamically available for use in one or more other partitions of the system, while the first partition retains ownership of the shared core(s). Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于将至少一个专用核和至少一个可共享核分配给系统的第一分区的方法，其中所述核由第一分区拥有。 在操作期间，可共享核心可以被动态地可用于在系统的一个或多个其他分区中使用，而第一分区保留共享核心的所有权。 描述和要求保护其他实施例。

公开(公告)号：US07389398B2

公开(公告)日：2008-06-17

申请号：US11300609

申请日：2005-12-14

申请人： John I. Garney

发明人： John I. Garney

IPC分类号： G06F12/10

CPC分类号： G06F9/5077

摘要： A method includes establishing two partitions, including a first partition and a second partition, in a computer system. The method further includes designating a first memory page in memory space controlled by the first partition, designating a second memory page in memory space controlled by the second partition, storing an address of the first memory page in an address mapping array that is accessible by the first partition and storing an address of the second memory page in an address mapping array that is accessible by the second partition. In addition, the method includes exchanging the address of the first memory page in the address mapping array that is accessible by the first partition with the address of the second memory page in the address mapping array that is accessible by the second partition.

摘要翻译： 一种方法包括在计算机系统中建立包括第一分区和第二分区的两个分区。 该方法还包括指定由第一分区控制的存储器空间中的第一存储器页面，指定由第二分区控制的存储器空间中的第二存储器页面，将第一存储器页面的地址存储在地址映射阵列中，该地址映射阵列可由 第一分区并将第二存储器页的地址存储在可由第二分区访问的地址映射阵列中。 此外，该方法包括将可由第一分区访问的地址映射数组中的第一存储器页的地址与可由第二分区访问的地址映射数组中的第二存储器页的地址进行交换。

公开(公告)号：US06952429B2

公开(公告)日：2005-10-04

申请号：US10613971

申请日：2003-07-03

申请人： John I. Garney ,  John S. Howard

发明人： John I. Garney ,  John S. Howard

IPC分类号： H04L12/417 ,  H04J3/24

CPC分类号： H04L12/4625 ,  H04L12/40013 ,  H04L12/4013 ,  H04L12/403 ,  H04L12/417

摘要： A method of and apparatus for communicating data using a hub. The method includes determining a first estimated unused capacity left in a first frame in which a second transaction is to be performed between a hub and an agent. The method then includes determining an amount of a first data that can fit into the estimated unused capacity and that is to be sent to the hub during a first transaction and then sent by the hub to the agent during the second transaction. The method also includes sending the first data to the hub during the first transaction.

摘要翻译： 一种使用集线器传送数据的方法和装置。 该方法包括确定在第一帧中剩下的第一估计未使用容量，其中将在轮毂和代理之间执行第二事务。 该方法然后包括确定可以适应于估计的未使用容量的第一数据的量，并且将在第一事务期间发送到集线器，然后由集线器在第二事务期间发送到代理。 该方法还包括在第一次交易期间将第一数据发送到集线器。

公开(公告)号：US06925015B2

公开(公告)日：2005-08-02

申请号：US10305588

申请日：2002-11-26

申请人： John I. Garney ,  David G. Chow ,  Rick Coulson

发明人： John I. Garney ,  David G. Chow ,  Rick Coulson

IPC分类号： G11C7/18 ,  H01L27/115 ,  G11C11/34

CPC分类号： H01L27/11502 ,  G11C7/18

摘要： Briefly, in accordance with one embodiment of the invention, a system includes a memory array. The memory array comprises a first layer of memory cells overlying a second layer of memory cells and bit lined coupled to at least one memory cell in the first layer of memory cells and to at least one memory cell in the second layer of memory cell.

摘要翻译： 简而言之，根据本发明的一个实施例，系统包括存储器阵列。 存储器阵列包括覆盖存储器单元的第二层的第一层存储器单元，以及耦合到第一层存储器单元中的至少一个存储器单元的位线和存储单元的第二层中的至少一个存储单元。

公开(公告)号：US06678761B2

公开(公告)日：2004-01-13

申请号：US09823798

申请日：2001-03-30

申请人： John I. Garney ,  John S. Howard

发明人： John I. Garney ,  John S. Howard

IPC分类号： G06F300

CPC分类号： G06F13/4059 ,  G06F2213/0042

摘要： A system and method for serial bus budget development and maintenance. The present invention relates to a method for budgeting transactions under a Universal Serial Bus (USB) protocol, utilizing split transactions, such as USB 2.0. The present invention provides for budgeting transactions occurring across a high-speed to full/low-speed translation, accommodating the full/low speed transactions as well as high-speed splits and data overhead in accordance with USB protocol.

摘要翻译： 一种用于串行总线预算开发和维护的系统和方法。 本发明涉及一种利用诸如USB2.0之类的分割事务在通用串行总线（USB）协议下预算交易的方法。 本发明提供了在高速到全/低速转换之间发生的预算交易，适应全/低速交易以及根据USB协议的高速分割和数据开销。

公开(公告)号：US06546018B1

公开(公告)日：2003-04-08

申请号：US09309484

申请日：1999-05-10

申请人： John I. Garney ,  John S. Howard ,  Venkat Iyer

发明人： John I. Garney ,  John S. Howard ,  Venkat Iyer

IPC分类号： H04J1500

CPC分类号： G06F13/385

摘要： A digital system is provided with a bus controller to operate and control a peripheral bus, wherein the bus controller selectively operates at least a first portion of the peripheral bus in a store-and-forward manner. The bus controller facilitates communication with a first bus agent in this first portion by sending a number of request packets destined for the first bus agent to a first hub in the first portion, in an integrated multi-packet form, in bulk, and at a first communication speed. The first hub buffers the request packets, and then forwards the request packets to the first bus agent, on a packet-by-packet basis, and at a second communication speed. In one embodiment, the second communication speed is slower than the first communication speed. In one embodiment, the first hub also receives communications destined for a second bus agent of this first portion, from the bus controller at the first communication speed, and repeats the communications for the second bus agent without buffering, at also the first communication speed. In another embodiment, the peripheral bus further includes a second portion, including a second hub that receives communications destined for a third bus agent in this second portion, from the bus controller at the second communication speed, and repeats the communications for the third bus agent without buffering, at also the second communication speed.

摘要翻译： 数字系统设置有总线控制器以操作和控制外围总线，其中总线控制器以存储和转发的方式选择性地操作外围总线的至少第一部分。 总线控制器通过以大量方式以集成的多分组形式向第一部分中的第一集线器发送目的地为第一总线代理的多个请求分组，并且在 第一通讯速度。 第一集线器缓冲请求分组，然后以逐个分组的方式，以第二通信速度将请求分组转发到第一总线代理。 在一个实施例中，第二通信速度比第一通信速度慢。 在一个实施例中，第一集线器还以第一通信速度从总线控制器接收目的地为该第一部分的第二总线代理的通信，并且也以第一通信速度重复第二总线代理的通信而不进行缓冲。 在另一个实施例中，外围总线还包括第二部分，包括第二集线器，第二集线器以第二通信速度从总线控制器接收发往第二部分中的第三总线代理的通信，并重复第三总线代理的通信 没有缓冲，也是第二个通信速度。

公开(公告)号：US06389501B1

公开(公告)日：2002-05-14

申请号：US09309087

申请日：1999-05-10

申请人： John I. Garney ,  John S. Howard ,  Venkat Iyer

发明人： John I. Garney ,  John S. Howard ,  Venkat Iyer

IPC分类号： G06F1312

CPC分类号： G06F13/4059

摘要： An I/O peripheral device is equipped with a first collection of circuitry to enable the I/O peripheral device to provide a store-and-forward manner of operation to a segment of a peripheral bus. The first collection of circuitry includes first buffering circuitry to buffer request packets destined for a first bus agent, received from a bus controller in an integrated multi-packet form, in bulk, and at a first communication speed. Furthermore, the first collection includes control circuitry to forward the request packets separately, in a packet-by-packet basis, to the first bus agent, in a second communication speed. In one embodiment, the second communication speed is slower than the first communication speed. The I/O peripheral device further includes second buffer circuitry to buffer response packets to a request from the first bus agent provided separately, and each at the slower second communication speed. The first control circuitry also facilitates forwarding of the buffered response packets to the bus controller in bulk at the faster first communication speed. In one embodiment, the I/O peripheral device further includes second control circuitry to repeat communications destined for a second bus agent, received from the bus controller at the first communication speed, for the second bus agent, at also the first communication speed. In one embodiment, the I/O peripheral device is a hub.

摘要翻译： I / O外围设备配备有电路的第一集合，以使得I / O外围设备能够向外围总线的段提供存储转发的操作方式。 电路的第一集合包括第一缓冲电路，用于以批量和第一通信速度缓冲以集成多分组形式从总线控制器接收的去往第一总线代理的请求分组。 此外，第一集合包括控制电路，其以第二通信速度逐个分组地将请求分组转发到第一总线代理。 在一个实施例中，第二通信速度比第一通信速度慢。 I / O外围设备还包括第二缓冲器电路，用于将响应分组缓冲到来自分开提供的第一总线代理的请求，并且每个以较慢的第二通信速度缓冲。 第一控制电路还有助于将缓冲的响应分组以更快的第一通信速度批量转发到总线控制器。 在一个实施例中，I / O外围设备还包括第二控制电路，用于以第一通信速度，以第一通信速度从总线控制器接收第二总线代理的第二总线代理用于第二总线代理。 在一个实施例中，I / O外围设备是集线器。