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    Energy efficient, robust differential mode d-flip-flop
    1.
    发明授权
    Energy efficient, robust differential mode d-flip-flop 有权

    公开(公告)号：US10250236B2

    公开(公告)日：2019-04-02

    申请号：US15575611

    申请日：2016-05-23

    申请人： Sarma Vrudhula ,  Niranjan Kulkarni ,  Jinghua Yang

    发明人： Sarma Vrudhula ,  Niranjan Kulkarni ,  Jinghua Yang

    IPC分类号： H03K3/037 ,  H03K3/012 ,  H03K3/356

    摘要： A differential sense flip flop (DSFF) that is named the Kulkarni Vrudhula flip flop (KVFF) is disclosed. In one embodiment, the DSFF includes a differential sense amplifier and an SR latch. The differential sense amplifier includes a first amplifier branch having a first output node, a second amplifier branch having a second, a first switchable discharge path, and a second switchable discharge path. The first switchable discharge path is closed to discharge the first output node when first output node is being discharged by the first amplifier branch and the second switchable discharge path is closed to discharge the second output node when second output node is being discharged by the second amplifier branch. This prevents the output nodes from floating and increases the reliability and robustness of the DSFF.

    Threshold logic gates with resistive networks
    2.
    发明授权
    Threshold logic gates with resistive networks 有权
    具有电阻网络的门限逻辑门

    公开(公告)号：US09356598B2

    公开(公告)日：2016-05-31

    申请号：US14792163

    申请日：2015-07-06

    申请人： Sarma Vrudhula ,  Jinghua Yang ,  Niranjan Kulkarni ,  Shimeng Yu

    发明人： Sarma Vrudhula ,  Jinghua Yang ,  Niranjan Kulkarni ,  Shimeng Yu

    IPC分类号： G11C7/06 ,  H03K19/23 ,  H03K19/00 ,  G11C13/00 ,  G06F17/50 ,  H03K19/08 ,  H03K19/017 ,  H03K19/21 ,  G11C17/16 ,  G11C17/18

    CPC分类号： H03K19/0013 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/12 ,  G11C7/065 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/004 ,  G11C17/165 ,  G11C17/18 ,  G11C2013/0042 ,  G11C2213/71 ,  G11C2213/79 ,  H03K19/0027 ,  H03K19/01707 ,  H03K19/0813 ,  H03K19/215 ,  Y02P90/265

    摘要： This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations.

    摘要翻译： 本公开一般涉及用于集成电路（IC）的阈值逻辑元件。 在一个实施例中，阈值逻辑元件具有第一输入门网络，第二输入门网络，差分读出放大器和电阻网络。 第一输入门网络被配置为接收第一组逻辑信号，而第二输入门网络被配置为接收第二组逻辑信号。 差分读出放大器可操作地与第一输入门网络和第二输入门网络相关联，使得差分读出放大器被配置为根据阈值逻辑功能产生差分输出。 电阻网络耦合在差分读出放大器和第一输入门网络之间以及差分读出放大器与第二输入门网络之间。 电阻网络使门限逻辑元件不易受工艺变化的影响。

    THRESHOLD LOGIC GATES WITH RESISTIVE NETWORKS
    3.
    发明申请
    THRESHOLD LOGIC GATES WITH RESISTIVE NETWORKS 有权
    带有电阻网络的门限逻辑门

    公开(公告)号：US20160006437A1

    公开(公告)日：2016-01-07

    申请号：US14792163

    申请日：2015-07-06

    申请人： Sarma Vrudhula ,  Jinghua Yang ,  Niranjan Kulkarni ,  Shimeng Yu

    发明人： Sarma Vrudhula ,  Jinghua Yang ,  Niranjan Kulkarni ,  Shimeng Yu

    IPC分类号： H03K19/00 ,  G11C13/00

    CPC分类号： H03K19/0013 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/12 ,  G11C7/065 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/004 ,  G11C17/165 ,  G11C17/18 ,  G11C2013/0042 ,  G11C2213/71 ,  G11C2213/79 ,  H03K19/0027 ,  H03K19/01707 ,  H03K19/0813 ,  H03K19/215 ,  Y02P90/265

    摘要： This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations.

    摘要翻译： 本公开一般涉及用于集成电路（IC）的阈值逻辑元件。 在一个实施例中，阈值逻辑元件具有第一输入门网络，第二输入门网络，差分读出放大器和电阻网络。 第一输入门网络被配置为接收第一组逻辑信号，而第二输入门网络被配置为接收第二组逻辑信号。 差分读出放大器可操作地与第一输入门网络和第二输入门网络相关联，使得差分读出放大器被配置为根据阈值逻辑功能产生差分输出。 电阻网络耦合在差分读出放大器和第一输入门网络之间以及差分读出放大器与第二输入门网络之间。 电阻网络使门限逻辑元件不易受工艺变化的影响。