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公开(公告)号：US08345491B2
公开(公告)日：2013-01-01
申请号：US13282331
申请日：2011-10-26
申请人： Satish K. Damaraju , Ak R. Ahmed , Scott E. Siers
发明人： Satish K. Damaraju , Ak R. Ahmed , Scott E. Siers
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , G11C11/419
摘要： Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and a complementary data node programming module configured to receive the second supply voltage and to program a complementary data node based at least in part on a complementary write data line, wherein the voltage module is configured such that the first supply voltage is substantially different from the second supply voltage for a period of time while the memory device is being programmed. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译： 存储单元的实施例包括被配置为提供第一电源电压和第二电源电压的电压模块，数据节点编程模块，被配置为接收第一电源电压并且至少部分地基于写数据线来编程数据节点 以及互补数据节点编程模块，其被配置为接收所述第二电源电压并且至少部分地基于互补写入数据线来编程互补数据节点，其中所述电压模块被配置为使得所述第一电源电压基本上不同于 第二电源电压在存储器件被编程期间一段时间。 也可以公开和要求保护附加的变型和实施例。
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公开(公告)号：US08050116B2
公开(公告)日：2011-11-01
申请号：US12564765
申请日：2009-09-22
申请人： Satish K. Damaraju , Ak R. Ahmed , Scott E. Siers
发明人： Satish K. Damaraju , Ak R. Ahmed , Scott E. Siers
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , G11C11/419
摘要： Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and a complementary data node programming module configured to receive the second supply voltage and to program a complementary data node based at least in part on a complementary write data line, wherein the voltage module is configured such that the first supply voltage is substantially different from the second supply voltage for a period of time while the memory device is being programmed. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译： 存储单元的实施例包括被配置为提供第一电源电压和第二电源电压的电压模块，数据节点编程模块，被配置为接收第一电源电压并且至少部分地基于写数据线来编程数据节点 以及互补数据节点编程模块，其被配置为接收所述第二电源电压并且至少部分地基于互补写入数据线来编程互补数据节点，其中所述电压模块被配置为使得所述第一电源电压基本上不同于 第二电源电压在存储器件被编程期间一段时间。 也可以公开和要求保护附加的变型和实施例。
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公开(公告)号：US20110069566A1
公开(公告)日：2011-03-24
申请号：US12564765
申请日：2009-09-22
申请人： Satish K. Damaraju , Ak R. Ahmed , Scott E. Siers
发明人： Satish K. Damaraju , Ak R. Ahmed , Scott E. Siers
CPC分类号： G11C11/412 , G11C11/419
摘要： Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and a complementary data node programming module configured to receive the second supply voltage and to program a complementary data node based at least in part on a complementary write data line, wherein the voltage module is configured such that the first supply voltage is substantially different from the second supply voltage for a period of time while the memory device is being programmed. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译： 存储单元的实施例包括被配置为提供第一电源电压和第二电源电压的电压模块，数据节点编程模块，被配置为接收第一电源电压并且至少部分地基于写数据线来编程数据节点 以及互补数据节点编程模块，其被配置为接收所述第二电源电压并且至少部分地基于互补写入数据线来编程互补数据节点，其中所述电压模块被配置为使得所述第一电源电压基本上不同于 第二电源电压在存储器件被编程期间一段时间。 也可以公开和要求保护附加的变型和实施例。
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公开(公告)号：US20120039135A1
公开(公告)日：2012-02-16
申请号：US13282331
申请日：2011-10-26
申请人： Satish K. Damaraju , Ak R. Ahmed , Scott E. Siers
发明人： Satish K. Damaraju , Ak R. Ahmed , Scott E. Siers
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , G11C11/419
摘要： Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and a complementary data node programming module configured to receive the second supply voltage and to program a complementary data node based at least in part on a complementary write data line, wherein the voltage module is configured such that the first supply voltage is substantially different from the second supply voltage for a period of time while the memory device is being programmed. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译： 存储单元的实施例包括被配置为提供第一电源电压和第二电源电压的电压模块，数据节点编程模块，被配置为接收第一电源电压并且至少部分地基于写数据线来编程数据节点 以及互补数据节点编程模块，其被配置为接收所述第二电源电压并且至少部分地基于互补写入数据线来编程互补数据节点，其中所述电压模块被配置为使得所述第一电源电压基本上不同于 第二电源电压在存储器件被编程期间一段时间。 也可以公开和要求保护附加的变型和实施例。
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5.发明申请PROCESSOR POWER CONSUMPTION CONTROL AND VOLTAGE DROP VIA MICRO-ARCHITECTURAL BANDWIDTH THROTTLING 审中-公开处理器消耗电力控制和电压降通过微结构带宽折射公开(公告)号：US20120210105A1
公开(公告)日：2012-08-16
申请号：US13212042
申请日：2011-08-17
IPC分类号： G06F9/30
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.
摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法包括向处理器提供第一电压。 该方法还包括允许处理器在第一电压下在增强的处理器停止状态下起作用。 第一电压是低于用于增强的处理器停止状态的最低兼容电压的电压。 该方法允许处理器在通过在处理器中执行的指令的最大吞吐速率从第一电压处的增强型处理器停止状态唤醒时执行指令。
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公开(公告)号：US06891400B2
公开(公告)日：2005-05-10
申请号：US10425594
申请日：2003-04-30
IPC分类号： H03K17/693 , H03K19/096 , H03K17/62 , H03K17/76 , H04J3/02
CPC分类号： H03K17/693
摘要： A Dual Rail Time Borrowing Multiplexer (DTBM) generates a dual rail output from a single rail input with a one gate equivalent delay using a negative set up time. In one embodiment, a multiplexer includes a cross-coupled differential domino circuit coupled to a transistor array and to a data input and an enable input through a first and second circuit. The multiplexer outputs a dual rail output corresponding to a selected data input with a one gate equivalent delay using a negative set up time.
摘要翻译： 双轨时间借用多路复用器（DTBM）使用负设置时间从单轨输入产生具有一个门等效延迟的双轨输出。 在一个实施例中，多路复用器包括耦合到晶体管阵列的交叉耦合差分多米诺骨架电路，以及通过第一和第二电路的数据输入和使能输入。 多路复用器使用负建立时间输出与具有一个门等效延迟的所选数据输入相对应的双轨输出。
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公开(公告)号：US06269386B1
公开(公告)日：2001-07-31
申请号：US09172933
申请日：1998-10-14
IPC分类号： G06F750
摘要： A 3x adder for adding 2a to a, where a is a binary number, the binary numbers 2a and a partitioned so that 2a=(xk . . . x0) and a=(yk . . . y0)where xi and yi have the same size for each i=0, 1, . . . , k, where the 3x adder provides the group generate terms for the sums xi+yi, i=0, 1, . . . , k, according to Boolean expressions, where for any sum xi+yi where xi and yi each have size n1+1, the number of Boolean variables in the product terms in the Boolean expression for the group generate terms of xi+yi do not exceed j+1, where j is the largest integer not exceeding ni/2.
摘要翻译： 一个3×加法器，用于将2a加到a，其中a是二进制数，二进制数2a和a被分割，使得2a =（xk。。x0）和a =（yk ... y0），其中xi和yi具有 每个i = 0，1，...相同的大小。 。 。 ，k，其中3x加法器为和xi + yi，i = 0,1，提供组生成项。 。 。 ，k，根据布尔表达式，其中对于任何和xi + yi，其中xi和yi各自具有大小n1 + 1，组中布尔表达式中乘积项中的布尔变量的数量生成xi + yi的项 超过j + 1，其中j是不超过ni / 2的最大整数。
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8.发明授权公开(公告)号：US08028181B2
公开(公告)日：2011-09-27
申请号：US12284303
申请日：2008-09-19
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.
摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法包括向处理器提供第一电压。 该方法还包括允许处理器在第一电压下在增强的处理器停止状态下起作用。 第一电压是低于用于增强的处理器停止状态的最低兼容电压的电压。 该方法允许处理器在通过在处理器中执行的指令的最大吞吐速率从第一电压处的增强型处理器停止状态唤醒时执行指令。
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9.发明申请公开(公告)号：US20100077232A1
公开(公告)日：2010-03-25
申请号：US12284303
申请日：2008-09-19
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.
摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法包括向处理器提供第一电压。 该方法还包括允许处理器在第一电压下在增强的处理器停止状态下起作用。 第一电压是低于用于增强的处理器停止状态的最低兼容电压的电压。 该方法允许处理器在通过在处理器中执行的指令的最大吞吐速率从第一电压处的增强型处理器停止状态唤醒时执行指令。
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公开(公告)号：US07269711B2
公开(公告)日：2007-09-11
申请号：US10747764
申请日：2003-12-29
申请人： Rajesh B. Patel , Robert L. Farrell , James E. Phillips , Belliappa Kuttanna , Scott E. Siers , T. W. Griffith
发明人： Rajesh B. Patel , Robert L. Farrell , James E. Phillips , Belliappa Kuttanna , Scott E. Siers , T. W. Griffith
IPC分类号： G06F12/00
CPC分类号： G06F9/342 , G06F9/355 , G06F9/3842 , G06F9/3861
摘要： Methods and apparatus to generate addresses in processors are disclosed. An example address generator disclosed herein includes an adder to add a first address component and a second address component to generate an address, a correction indicator to indicate if the address is correct, and a control input to modify an operation of the adder.
摘要翻译： 公开了在处理器中产生地址的方法和装置。 本文公开的示例性地址生成器包括：加法器，用于添加第一地址分量和第二地址分量以产生地址;校正指示符，用于指示地址是否正确;以及控制输入，用于修改加法器的操作。
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