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公开(公告)号：US07778075B2
公开(公告)日：2010-08-17
申请号：US12425018
申请日：2009-04-16
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/1202 , G11C2029/1204
摘要： A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.
摘要翻译： 半导体存储器件包括具有电路结构的存储单元，其中提供给包含在锁存部分中的负载晶体管108和111的源极的电位与提供给字线105的电位和提供给字线105的电位中的至少一个不同 位线106和107; 锁存电位控制电路101，用于根据施加到测试模式设置引脚102的信号将正常操作模式和测试模式切换到彼此; 以及用于控制提供给负载晶体管108和111的源的电位低于提供给字线105的电位和提供给位线106和107的电位中的至少一个的读/写控制电路103 在测试模式下至少读取操作的任意时段期间。
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公开(公告)号：US07542368B2
公开(公告)日：2009-06-02
申请号：US11634110
申请日：2006-12-06
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/1202 , G11C2029/1204
摘要： A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.
摘要翻译： 半导体存储器件包括具有电路结构的存储单元，其中提供给包含在锁存部分中的负载晶体管108和111的源极的电位与提供给字线105的电位和提供给字线105的电位中的至少一个不同 位线106和107; 锁存电位控制电路101，用于根据施加到测试模式设置引脚102的信号将正常操作模式和测试模式切换到彼此; 以及用于控制提供给负载晶体管108和111的源的电位低于提供给字线105的电位和提供给位线106和107的电位中的至少一个的读/写控制电路103 在测试模式下至少读取操作的任意时段期间。
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公开(公告)号：US20100277991A1
公开(公告)日：2010-11-04
申请号：US12838119
申请日：2010-07-16
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/1202 , G11C2029/1204
摘要： A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.
摘要翻译： 半导体存储器件包括具有电路结构的存储单元，其中提供给包含在锁存部分中的负载晶体管108和111的源极的电位与提供给字线105的电位和提供给字线105的电位中的至少一个不同 位线106和107; 锁存电位控制电路101，用于根据施加到测试模式设置引脚102的信号将正常操作模式和测试模式切换到彼此; 以及用于控制提供给负载晶体管108和111的源的电位低于提供给字线105的电位和提供给位线106和107的电位中的至少一个的读/写控制电路103 在测试模式下至少读取操作的任意时段期间。
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公开(公告)号：US20090201745A1
公开(公告)日：2009-08-13
申请号：US12425018
申请日：2009-04-16
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/1202 , G11C2029/1204
摘要： A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.
摘要翻译： 半导体存储器件包括具有电路结构的存储单元，其中提供给包含在锁存部分中的负载晶体管108和111的源极的电位与提供给字线105的电位和提供给字线105的电位中的至少一个不同 位线106和107; 锁存电位控制电路101，用于根据施加到测试模式设置引脚102的信号将正常操作模式和测试模式切换到彼此; 以及用于控制提供给负载晶体管108和111的源的电位低于提供给字线105的电位和提供给位线106和107的电位中的至少一个的读/写控制电路103 在测试模式下至少读取操作的任意时段期间。
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公开(公告)号：US20070133326A1
公开(公告)日：2007-06-14
申请号：US11634110
申请日：2006-12-06
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/1202 , G11C2029/1204
摘要： A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.
摘要翻译： 半导体存储器件包括具有电路结构的存储单元，其中提供给包含在锁存部分中的负载晶体管108和111的源极的电位与提供给字线105的电位和提供给字线105的电位中的至少一个不同 位线106和107; 锁存电位控制电路101，用于根据施加到测试模式设置引脚102的信号将正常操作模式和测试模式切换到彼此; 以及用于控制提供给负载晶体管108和111的源的电位低于提供给字线105的电位和提供给位线106和107的电位中的至少一个的读/写控制电路103 在测试模式下至少读取操作的任意时段期间。
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公开(公告)号：US08077530B2
公开(公告)日：2011-12-13
申请号：US13084026
申请日：2011-04-11
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括用于保持存储器数据的保持电路，以及一个只读输出电路，用于输出与由保持电路保持的数据相对应的信号。 只读输出电路具有根据由保持电路保持的信号控制的读驱动晶体管。 读取驱动晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。 或者，只读输出电路具有根据读取字选择信号控制的读取存取晶体管，并且读取存取晶体管的栅极长度比包含在保持电路中的晶体管的栅极长度长。
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公开(公告)号：US07692955B2
公开(公告)日：2010-04-06
申请号：US12039585
申请日：2008-02-28
IPC分类号： G11C11/00
摘要： A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor.
摘要翻译： 半导体集成电路包括：包括多个SRAM存储单元的存储单元阵列; 包括并联连接的多个晶体管电路的特性测量电路; 和第一个终端。 多个晶体管电路各自包括以与包括在SRAM存储单元之一中的晶体管中的一个相同的方式配置的第一晶体管。 第一晶体管被连接以便根据提供给第一晶体管的栅极的电压来控制第一端子和参考电位的节点之间的电流。
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公开(公告)号：US08014191B2
公开(公告)日：2011-09-06
申请号：US12352838
申请日：2009-01-13
IPC分类号： G11C11/00
CPC分类号： G11C5/14 , G11C11/412
摘要： In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to memory cells provided on a corresponding one of the bit lines. In a write operation, the bit line precharge circuit controls the potential of a low-data holding power supply of a memory cell corresponding to a selected bit line to be higher than the potential of a low-data holding power supply of a memory cell corresponding to an unselected bit line.
摘要翻译： 在包括排列成矩阵的字线和位线的半导体存储器以及设置在字线和位线的交叉处的多个存储单元的情况下，提供位线预充电电路，用于控制低数据保持电力的电位 电源耦合到提供在对应的一个位线上的存储器单元。 在写入操作中，位线预充电电路控制与所选位线对应的存储单元的低数据保持电源的电位高于对应于存储单元的低数据保持电源的电位 到未选择的位线。
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公开(公告)号：US20110188327A1
公开(公告)日：2011-08-04
申请号：US13084026
申请日：2011-04-11
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C8/16 , G11C29/12
摘要： A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.
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公开(公告)号：US20080253171A1
公开(公告)日：2008-10-16
申请号：US12039585
申请日：2008-02-28
IPC分类号： G11C11/00
摘要： A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor.
摘要翻译： 半导体集成电路包括：包括多个SRAM存储单元的存储单元阵列; 包括并联连接的多个晶体管电路的特性测量电路; 和第一个终端。 多个晶体管电路各自包括以与包括在SRAM存储单元之一中的晶体管中的一个相同的方式配置的第一晶体管。 第一晶体管被连接以便根据提供给第一晶体管的栅极的电压来控制第一端子和参考电位的节点之间的电流。
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