公开(公告)号：US20110215830A1

公开(公告)日：2011-09-08

申请号：US13106926

申请日：2011-05-13

申请人： Satoshi MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

发明人： Satoshi MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

IPC分类号： H03K19/003

CPC分类号： H03K19/018521

摘要： An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.

摘要翻译： 输出缓冲器包括反相器，用于延迟输入信号的延迟电路，缓冲器和开关。 输出缓冲器将逻辑信号发送到传输路径，并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。 缓冲器并联冗余连接，同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。 通过选择接通的开关的缓冲器，通过选择器逻辑选择信号调整预加重量和预加重抽头数，使预加重量变为可变，并使缓冲器的导通电阻保持恒定。

公开(公告)号：US20100219856A1

公开(公告)日：2010-09-02

申请号：US12716796

申请日：2010-03-03

申请人： Satoshi MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

发明人： Satoshi MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

IPC分类号： H03K19/003 ,  H03K19/094

CPC分类号： H03K19/018521

摘要： In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.

摘要翻译： 在包括变频器1至变频器3的输出缓冲电路中，延迟电路1至延迟电路3用于将输入信号延迟特定时间，缓冲器1至缓冲器3，以及用于将逻辑信号发送到传输路径的功能 在传输路径中具有一定量的信号衰减，在发送侧产生包括四种或更多种信号电压的波形，使预加重量变为可变，并使缓冲器的导通电阻Rs保持恒定。 选择器电路1至选择器电路3位于缓冲器之前，反相器能够通过选择器逻辑选择要输入到缓冲器的信号，反转数据信号，并且预加重量和预加重数量通过一个 选择器逻辑的选择信号。

公开(公告)号：US08324925B2

公开(公告)日：2012-12-04

申请号：US13106926

申请日：2011-05-13

申请人： Satoshi Muraoka ,  Norio Chujo ,  Ritsuro Orihashi

发明人： Satoshi Muraoka ,  Norio Chujo ,  Ritsuro Orihashi

IPC分类号： H03K19/003

CPC分类号： H03K19/018521

摘要： An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.

摘要翻译： 输出缓冲器包括反相器，用于延迟输入信号的延迟电路，缓冲器和开关。 输出缓冲器将逻辑信号发送到传输路径，并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。 缓冲器并联冗余连接，同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。 通过选择接通的开关的缓冲器，通过选择器逻辑选择信号调整预加重量和预加重抽头数，使预加重量变为可变，并使缓冲器的导通电阻保持恒定。

公开(公告)号：US07692445B2

公开(公告)日：2010-04-06

申请号：US11686560

申请日：2007-03-15

申请人： Satoshi Muraoka ,  Norio Chujo ,  Ritsuro Orihashi

发明人： Satoshi Muraoka ,  Norio Chujo ,  Ritsuro Orihashi

IPC分类号： H03K19/003

CPC分类号： H03K19/018521

摘要： In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.

摘要翻译： 在包括变频器1至变频器3的输出缓冲电路中，延迟电路1至延迟电路3用于将输入信号延迟特定时间，缓冲器1至缓冲器3，以及用于将逻辑信号发送到传输路径的功能 在传输路径中具有一定量的信号衰减，在发送侧产生包括四种或更多种信号电压的波形，使预加重量变为可变，并使缓冲器的导通电阻Rs保持恒定。 选择器电路1至选择器电路3位于缓冲器之前，反相器能够通过选择器逻辑选择要输入到缓冲器的信号，反转数据信号，并且预加重量和预加重数量通过一个 选择器逻辑的选择信号。

公开(公告)号：US07969197B2

公开(公告)日：2011-06-28

申请号：US12716796

申请日：2010-03-03

申请人： Satoshi Muraoka ,  Norio Chujo ,  Ritsuro Orihashi

发明人： Satoshi Muraoka ,  Norio Chujo ,  Ritsuro Orihashi

IPC分类号： H03K19/094

CPC分类号： H03K19/018521

摘要： An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.

摘要翻译： 输出缓冲器包括反相器，用于延迟输入信号的延迟电路，缓冲器和开关。 输出缓冲器将逻辑信号发送到传输路径，并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。 缓冲器并联冗余连接，同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。 通过选择接通的开关的缓冲器，通过选择器逻辑选择信号调整预加重量和预加重抽头数，使预加重量变为可变，并使缓冲器的导通电阻保持恒定。

公开(公告)号：US20080265944A1

公开(公告)日：2008-10-30

申请号：US11686560

申请日：2007-03-15

申请人： SATOSHI MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

发明人： SATOSHI MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

IPC分类号： H03K19/0185 ,  H03K19/0175

CPC分类号： H03K19/018521

摘要： In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.

摘要翻译： 在包括变频器1至变频器3的输出缓冲电路中，延迟电路1至延迟电路3用于将输入信号延迟特定时间，缓冲器1至缓冲器3，以及用于将逻辑信号发送到传输路径的功能 在传输路径中具有一定量的信号衰减，在发送侧产生包括四种或更多种信号电压的波形，使预加重量变为可变，并使缓冲器的导通电阻Rs保持恒定。 选择器电路1至选择器电路3位于缓冲器之前，反相器能够通过选择器逻辑选择要输入到缓冲器的信号，反转数据信号，并且预加重量和预加重数量通过一个 选择器逻辑的选择信号。

公开(公告)号：US07358953B2

公开(公告)日：2008-04-15

申请号：US10714943

申请日：2003-11-18

申请人： Masami Makuuchi ,  Kengo Imagawa ,  Norio Chujo ,  Ritsuro Orihashi ,  Yoshitomo Arai ,  Atsushi Obuchi

发明人： Masami Makuuchi ,  Kengo Imagawa ,  Norio Chujo ,  Ritsuro Orihashi ,  Yoshitomo Arai ,  Atsushi Obuchi

IPC分类号： G09G3/36

CPC分类号： G09G3/006 ,  G09G3/3648 ,  G09G5/006 ,  G09G5/39 ,  G09G2310/027 ,  Y10S345/904

摘要： A semiconductor device having a liquid crystal driving circuit is disclosed. The driving circuit includes a digital functional unit and an analog functional unit. The digital functional unit is comprised of a display controller and a display data storage RAM, while the analog functional unit is made up of a gradation voltage generating circuit and a gradation voltage selecting circuit. The digital and analog function units are functionally divided from each other and testing of the digital function and testing of the analog function unit are performed in an overlapping manner independently from each other.

摘要翻译： 公开了一种具有液晶驱动电路的半导体器件。 驱动电路包括数字功能单元和模拟功能单元。 数字功能单元包括显示控制器和显示数据存储RAM，而模拟功能单元由灰度电压产生电路和灰度电压选择电路组成。 数字和模拟功能单元在功能上彼此划分，并且以彼此独立的重叠方式执行数字功能的测试和模拟功能单元的测试。

公开(公告)号：US20050122300A1

公开(公告)日：2005-06-09

申请号：US10981715

申请日：2004-11-05

申请人： Masami Makuuchi ,  Norio Chujo ,  Kengo Imagawa ,  Ritsuro Orihashi ,  Yoshitomo Arai

发明人： Masami Makuuchi ,  Norio Chujo ,  Kengo Imagawa ,  Ritsuro Orihashi ,  Yoshitomo Arai

IPC分类号： G01R31/316 ,  G01R31/28 ,  G02F1/133 ,  G09G3/00 ,  G09G3/20 ,  G09G3/36 ,  H01L21/822 ,  H01L27/04

CPC分类号： G09G3/006 ,  G09G3/3688

摘要： A semiconductor device according to the present invention has a liquid crystal driver circuit, and when gray-scale voltage thereof is tested, the gray-scale voltage (Vx) generated in a gray-scale voltage generator circuit provided therein is compared with reference voltage (e.g., Vx+ΔV) generated for testing the gray-scale voltage and the test result is output as binarized voltage from external terminals of the semiconductor device. This can speed up the gray-scale voltage test even in the case of higher gray scale in the liquid crystal driver circuit or increased number of output terminals of the semiconductor device. Therefore, it becomes possible to reduce the time and cost required for the test.

摘要翻译： 根据本发明的半导体器件具有液晶驱动电路，并且当其灰度电压被测试时，在其中提供的灰度级电压发生器电路中产生的灰度电压（Vx）与参考电压（ 例如，用于测试灰度电压而生成的Vx + DeltaV）和测试结果作为来自半导体器件的外部端子的二值化电压输出。 即使在液晶驱动电路中较高的灰度级或半导体器件的输出端数量增加的情况下，也可以加快灰度电压测试。 因此，可以减少测试所需的时间和成本。

公开(公告)号：US07474290B2

公开(公告)日：2009-01-06

申请号：US10981715

申请日：2004-11-05

申请人： Masami Makuuchi ,  Norio Chujo ,  Kengo Imagawa ,  Ritsuro Orihashi ,  Yoshitomo Arai

发明人： Masami Makuuchi ,  Norio Chujo ,  Kengo Imagawa ,  Ritsuro Orihashi ,  Yoshitomo Arai

IPC分类号： G09G3/36

CPC分类号： G09G3/006 ,  G09G3/3688

摘要： A semiconductor device according to the present invention has a liquid crystal driver circuit, and when gray-scale voltage thereof is tested, the gray-scale voltage (Vx) generated in a gray-scale voltage generator circuit provided therein is compared with reference voltage (e.g., Vx+ΔV) generated for testing the gray-scale voltage and the test result is output as binarized voltage from external terminals of the semiconductor device. This can speed up the gray-scale voltage test even in the case of higher gray scale in the liquid crystal driver circuit or increased number of output terminals of the semiconductor device. Therefore, it becomes possible to reduce the time and cost required for the test.

摘要翻译： 根据本发明的半导体器件具有液晶驱动电路，并且当其灰度电压被测试时，在其中提供的灰度级电压发生器电路中产生的灰度电压（Vx）与参考电压（ 例如，用于测试灰度电压而生成的Vx + DeltaV）和测试结果作为来自半导体器件的外部端子的二值化电压输出。 即使在液晶驱动电路中较高的灰度级或半导体器件的输出端数量增加的情况下，也可以加快灰度电压测试。 因此，可以减少测试所需的时间和成本。

公开(公告)号：US07443373B2

公开(公告)日：2008-10-28

申请号：US11002143

申请日：2004-12-03

申请人： Kengo Imagawa ,  Masami Makuuchi ,  Norio Chujo ,  Ritsuro Orihashi ,  Yoshitomo Arai

发明人： Kengo Imagawa ,  Masami Makuuchi ,  Norio Chujo ,  Ritsuro Orihashi ,  Yoshitomo Arai

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/006 ,  G09G2310/0289

摘要： A problem, which one of the inventions included in the present application solves, is to provide a semiconductor device that can simultaneously test a plurality of output pins by less channels of a semiconductor test equipment in number than the integrated output pins of the semiconductor device. Representative one of the inventions has such a configuration that an LCD driver, which is the semiconductor device having a function of driving a gate line of a liquid crystal display panel, comprises: an exclusive-OR circuit for inverting polarities of positive and negative voltages for driving the gate line; a tri-state type inverter circuit capable of changing and controlling, to a high-impedance state, an output circuit for driving the gate line; and at least one of test control terminals TEST for controlling the exclusive-OR circuit and the tri-state type inverter circuit. When a test is conducted, only one terminal of the gate output outputs a positive voltage VGH or negative voltage VGL and the other terminal is set to a high-impedance state, whereby the plurality of gate outputs are simultaneously tested.

摘要翻译： 包括在本申请中的发明中的一个解决的问题是提供一种半导体器件，其可以通过半导体测试设备的数量少于半导体器件的集成输出引脚的较少通道同时测试多个输出引脚。 代表性的发明之一具有这样的结构，即作为具有驱动液晶显示面板的栅极线的功能的半导体器件的LCD驱动器包括：用于将正和负电压的极性反转的异或电路， 驾驶门线; 能够改变和控制高阻抗状态的用于驱动栅极线的输出电路的三态逆变器电路; 以及用于控制异或电路和三态逆变器电路的测试控制端子TEST中的至少一个。 当进行测试时，仅栅极输出的一个端子输出正电压VGH或负电压VGL，另一个端子被设置为高阻抗状态，从而同时测试多个栅极输出。