公开(公告)号：US20110215830A1

公开(公告)日：2011-09-08

申请号：US13106926

申请日：2011-05-13

申请人： Satoshi MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

发明人： Satoshi MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

IPC分类号： H03K19/003

CPC分类号： H03K19/018521

摘要： An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.

摘要翻译： 输出缓冲器包括反相器，用于延迟输入信号的延迟电路，缓冲器和开关。 输出缓冲器将逻辑信号发送到传输路径，并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。 缓冲器并联冗余连接，同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。 通过选择接通的开关的缓冲器，通过选择器逻辑选择信号调整预加重量和预加重抽头数，使预加重量变为可变，并使缓冲器的导通电阻保持恒定。

公开(公告)号：US20100219856A1

公开(公告)日：2010-09-02

申请号：US12716796

申请日：2010-03-03

申请人： Satoshi MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

发明人： Satoshi MURAOKA ,  Norio Chujo ,  Ritsuro Orihashi

IPC分类号： H03K19/003 ,  H03K19/094

CPC分类号： H03K19/018521

摘要： In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.

摘要翻译： 在包括变频器1至变频器3的输出缓冲电路中，延迟电路1至延迟电路3用于将输入信号延迟特定时间，缓冲器1至缓冲器3，以及用于将逻辑信号发送到传输路径的功能 在传输路径中具有一定量的信号衰减，在发送侧产生包括四种或更多种信号电压的波形，使预加重量变为可变，并使缓冲器的导通电阻Rs保持恒定。 选择器电路1至选择器电路3位于缓冲器之前，反相器能够通过选择器逻辑选择要输入到缓冲器的信号，反转数据信号，并且预加重量和预加重数量通过一个 选择器逻辑的选择信号。

公开(公告)号：US20120194304A1

公开(公告)日：2012-08-02

申请号：US13354436

申请日：2012-01-20

申请人： Satoshi MURAOKA

发明人： Satoshi MURAOKA

IPC分类号： H04B3/14

CPC分类号： H04L25/03878 ,  H04B3/04 ,  H05K1/0233 ,  H05K1/0251 ,  H05K2201/086

摘要： An equalizer circuit includes a passive equalizer having an inductor connected in parallel to a signal interconnection line, the inductor being made up of a conductor portion formed on a side face of a through-hole of a circuit board.

摘要翻译： 均衡器电路包括具有与信号互连线并联连接的电感器的无源均衡器，电感器由形成在电路板的通孔的侧面上的导体部分构成。

公开(公告)号：US20160188511A1

公开(公告)日：2016-06-30

申请号：US14423769

申请日：2014-04-25

申请人： Satoshi MURAOKA ,  Keisuke HATASAKI ,  Mutsumi HOSOYA ,  Yasunori KANEDA ,  Toshihiro ISHIKI

发明人： Satoshi MURAOKA ,  Keisuke HATASAKI ,  Mutsumi HOSOYA ,  Yasunori KANEDA ,  Toshihiro ISHIKI

IPC分类号： G06F13/364 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F13/364 ,  G06F13/4022 ,  G06F13/4282

摘要： A computer system includes a switch having a plurality of ports, a plurality of devices coupled to the plurality of ports, and a management system coupled to at least one of the plurality of devices and the switch. The coupling between the plurality of devices and the switch is a communication interface in which the number of master devices capable of existing in the same space is defined. The management system collects device coupling data of each of the plurality of devices coupled to the switch. Each of the device coupling data includes an ID of a port to which the device is coupled and information representing an attribute indicating whether the device is a master or a slave. The management system determines a coupling configuration on the basis of the plurality of the collected device coupling data and a communication interface protocol and, configures, to the switch, coupling information that is information in accordance with the determined coupling configuration.

摘要翻译： 计算机系统包括具有多个端口的交换机，耦合到多个端口的多个设备，以及耦合到多个设备和交换机中的至少一个的管理系统。 多个设备和交换机之间的耦合是其中能够存在于相同空间中的主设备的数量被定义的通信接口。 管理系统收集耦合到交换机的多个设备中的每一个的设备耦合数据。 每个设备耦合数据包括设备耦合到的端口的ID和表示设备是主设备还是从设备的属性的信息。 管理系统基于多个收集的设备耦合数据和通信接口协议来确定耦合配置，并且根据所确定的耦合配置向交换机配置作为信息的耦合信息。

公开(公告)号：US20110234249A1

公开(公告)日：2011-09-29

申请号：US13044717

申请日：2011-03-10

申请人： Yutaka UEMATSU ,  Hideki OSAKA ,  Satoshi NAKAMURA ,  Satoshi MURAOKA ,  Mitsuaki KATAGIRI ,  Ken IWAKURA ,  Yukitoshi HIROSE

发明人： Yutaka UEMATSU ,  Hideki OSAKA ,  Satoshi NAKAMURA ,  Satoshi MURAOKA ,  Mitsuaki KATAGIRI ,  Ken IWAKURA ,  Yukitoshi HIROSE

IPC分类号： G01R31/00

CPC分类号： G01R31/2889

摘要： An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

摘要翻译： 安装有作为测试对象的集成电路的插入器设置有用于检测与集成电路的各个端子相对应的电流的开关和探头。 然后，通过作为与集成电路的电源端子连接并断开的开关的测试基板将测试图形信号输入到集成电路。 如果集成电路正常工作，并且集成电路的所有端子的电流值都在容差内，则连接到关断开关的电源端子被识别为可以被去除的端子。

公开(公告)号：US20110007487A1

公开(公告)日：2011-01-13

申请号：US12815399

申请日：2010-06-15

申请人： Satoshi MURAOKA

发明人： Satoshi MURAOKA

IPC分类号： H05K7/00

CPC分类号： H01L23/49838 ,  H01L23/552 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A technology capable of reducing a crosstalk noise generated between through holes of an LSI package and a printed board at low cost is provided. In an electronic device in which an LSI package is mounted on a printed board, a plurality of transmission terminals and a plurality of reception terminals are provided, and the plurality of transmission terminals include transmission terminal pairs which transmit a differential signal and the plurality of reception terminals include reception terminal pairs which receive the differential signal. In the LSI package, two transmission terminal pairs and two reception terminal pairs are respectively adjacent to each other and are arranged so that a line which connects the terminals of one pair intersects with a line which connects the terminals of the other pair.

摘要翻译： 提供了能够以低成本降低在LSI封装的通孔和印刷电路板之间产生的串扰噪声的技术。 在将LSI封装安装在印刷电路板上的电子设备中，设置有多个发送终端和多个接收终端，多个发送终端包括发送差分信号和多个接收的发送终端对 终端包括接收差分信号的接收终端对。 在LSI封装中，两个发送端子对和两个接收端子对分别相邻并且被布置成使得连接一对的端子的线与连接另一对的端子的线相交。

公开(公告)号：US20120302075A1

公开(公告)日：2012-11-29

申请号：US13481013

申请日：2012-05-25

申请人： Satoshi MURAOKA ,  Masayoshi YAGYU

发明人： Satoshi MURAOKA ,  Masayoshi YAGYU

IPC分类号： H05K1/11 ,  H01R12/00

CPC分类号： H05K1/0251 ,  H05K1/115 ,  H05K3/0047 ,  H05K2201/10295 ,  H05K2203/0207

摘要： The present invention maintains plugging-unplugging durability of connector pins for connecting to a signal wiring board, as well as reduces a stub length of a through hole connecting to a signal wiring. In the signal wiring board according to the present invention, a through hole connecting to the inner-layer signal wiring is formed to be shorter than the other through holes. A through hole in which a connector pin connecting to the inner-layer signal wiring is inserted is formed to have a length corresponding to a depth of the inner-layer signal wiring.

摘要翻译： 本发明保持用于连接到信号线路板的连接器针的插拔耐久性，并且减少连接到信号线的通孔的短截线长度。 在根据本发明的信号线路板中，连接到内层信号线的通孔形成为比其他通孔短。 其中插入连接到内层信号布线的连接器针的通孔形成为具有与内层信号布线的深度对应的长度。

公开(公告)号：US20120112849A1

公开(公告)日：2012-05-10

申请号：US13004609

申请日：2011-01-11

申请人： Yasuhiro IKEDA ,  Yutaka UEMATSU ,  Satoshi MURAOKA

发明人： Yasuhiro IKEDA ,  Yutaka UEMATSU ,  Satoshi MURAOKA

IPC分类号： H03H2/00 ,  H03H7/38

CPC分类号： H04B3/02

摘要： A data transmission system is provided in which it is possible to perform both of suppressing the degrading of the slew rate and suppressing the ringing even if load capacitance of an input buffer is changed.The data transmission system transmitting data from an output buffer to the input buffer through a trace is provided with first RC parallel circuits connected in series to the trace on a first Printed Circuit Board (PCB) on which the output buffer is mounted, and second RC parallel circuits connected in series to the trace on a second Printed Circuit Board (PCB) on which the input buffer is mounted, and which can be connected and separated to and from the first Printed Circuit Board (PCB).

摘要翻译： 提供了一种数据传输系统，其中即使输入缓冲器的负载电容改变，也可以同时执行抑制转换速率的降级和抑制振铃的两者。 通过轨迹将数据从输出缓冲器传输到输入缓冲器的数据传输系统提供有与其上安装有输出缓冲器的第一印刷电路板（PCB）上的迹线串联连接的第一RC并联电路，以及第二RC 并联电路与安装有输入缓冲器的第二印刷电路板（PCB）上的迹线串联连接，并且可以与第一个印刷电路板（PCB）连接和分离。