公开(公告)号：US08053317B2

公开(公告)日：2011-11-08

申请号：US12541933

申请日：2009-08-15

申请人： Satya N. Chakravarti ,  Dechao Guo ,  Wilfried Ernst-August Haensch ,  Pranita Kulkarni ,  Fei Liu ,  Philip J. Oldiges ,  Keith Kwong Hon Wong

发明人： Satya N. Chakravarti ,  Dechao Guo ,  Wilfried Ernst-August Haensch ,  Pranita Kulkarni ,  Fei Liu ,  Philip J. Oldiges ,  Keith Kwong Hon Wong

IPC分类号： H01L21/8234

CPC分类号： H01L27/0629 ,  H01L21/82345

摘要： Method of forming a semiconductor device which includes the steps of obtaining a semiconductor substrate having a logic region and an STI region; sequentially depositing layers of high K material, metal gate, first silicon and hardmask; removing the hardmask and first silicon layers from the logic region; applying a second layer of silicon on the semiconductor substrate such that the logic region has layers of high K material, metal gate and second silicon and the STI region has layers of high K material, metal gate, first silicon, hardmask and second silicon. There may also be a second hardmask layer between the metal gate layer and the first silicon layer in the STI region. There may also be a hardmask layer between the metal gate layer and the first silicon layer in the STI region but no hardmask layer between the first and second layers of silicon in the STI region.

摘要翻译： 形成半导体器件的方法包括以下步骤：获得具有逻辑区域和STI区域的半导体衬底; 依次沉积高K材料，金属栅极，第一硅和硬掩模层; 从逻辑区域去除硬掩模和第一硅层; 在半导体衬底上施加第二层硅，使得逻辑区域具有高K材料，金属栅极和第二硅层，并且STI区域具有高K材料，金属栅极，第一硅，硬掩模和第二硅层。 也可以在STI区域中的金属栅极层和第一硅层之间存在第二硬掩模层。 在STI区域中的金属栅极层和第一硅层之间也可以存在硬掩模层，但在STI区域中的第一和第二硅层之间没有硬掩模层。

公开(公告)号：US20110037128A1

公开(公告)日：2011-02-17

申请号：US12541933

申请日：2009-08-15

申请人： Satya N. Chakravarti ,  Dechao Guo ,  Wilfried Ernst-August Haensch ,  Pranita Kulkarni ,  Fei Liu ,  Philip J. Oldiges ,  Keith Kwong Hon Wong

发明人： Satya N. Chakravarti ,  Dechao Guo ,  Wilfried Ernst-August Haensch ,  Pranita Kulkarni ,  Fei Liu ,  Philip J. Oldiges ,  Keith Kwong Hon Wong

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L27/0629 ,  H01L21/82345

摘要： Method of forming a semiconductor device which includes the steps of obtaining a semiconductor substrate having a logic region and an STI region; sequentially depositing layers of high K material, metal gate, first silicon and hardmask; removing the hardmask and first silicon layers from the logic region; applying a second layer of silicon on the semiconductor substrate such that the logic region has layers of high K material, metal gate and second silicon and the STI region has layers of high K material, metal gate, first silicon, hardmask and second silicon. There may also be a second hardmask layer between the metal gate layer and the first silicon layer in the STI region. There may also be a hardmask layer between the metal gate layer and the first silicon layer in the STI region but no hardmask layer between the first and second layers of silicon in the STI region.

摘要翻译： 形成半导体器件的方法包括以下步骤：获得具有逻辑区域和STI区域的半导体衬底; 依次沉积高K材料，金属栅极，第一硅和硬掩模层; 从逻辑区域去除硬掩模和第一硅层; 在半导体衬底上施加第二层硅，使得逻辑区域具有高K材料，金属栅极和第二硅层，并且STI区域具有高K材料，金属栅极，第一硅，硬掩模和第二硅层。 也可以在STI区域中的金属栅极层和第一硅层之间存在第二硬掩模层。 在STI区域中的金属栅极层和第一硅层之间也可以存在硬掩模层，但在STI区域中的第一和第二硅层之间没有硬掩模层。

公开(公告)号：US08288217B2

公开(公告)日：2012-10-16

申请号：US12945026

申请日：2010-11-12

申请人： Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Alexander Reznicek ,  Keith Kwong Hon Wong

发明人： Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Alexander Reznicek ,  Keith Kwong Hon Wong

IPC分类号： H01L21/338

CPC分类号： H01L29/66545 ,  H01L29/1054 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/7843 ,  H01L29/7848

摘要： A field effect transistor device includes a gate stack portion disposed on a substrate, and a channel region in the substrate having a depth partially defined by the gate stack portion and a silicon region of the substrate, the silicon region having a sloped profile such that a distal regions of the channel region have greater depth than a medial region of the channel region.

摘要翻译： 场效应晶体管器件包括设置在衬底上的栅极堆叠部分和衬底中的沟道区域，其具有由栅极堆叠部分和衬底的硅区域部分地限定的深度，所述硅区域具有倾斜轮廓，使得 沟道区域的远侧区域具有比沟道区域的中间区域更深的深度。

公开(公告)号：US20120119266A1

公开(公告)日：2012-05-17

申请号：US12945026

申请日：2010-11-12

申请人： Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Alexander Reznicek ,  Keith Kwong Hon Wong

发明人： Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Alexander Reznicek ,  Keith Kwong Hon Wong

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/1054 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/7843 ,  H01L29/7848

摘要： A field effect transistor device includes a gate stack portion disposed on a substrate, and a channel region in the substrate having a depth partially defined by the gate stack portion and a silicon region of the substrate, the silicon region having a sloped profile such that a distal regions of the channel region have greater depth than a medial region of the channel region.

摘要翻译： 场效应晶体管器件包括设置在衬底上的栅极堆叠部分和衬底中的沟道区域，其具有由栅极堆叠部分和衬底的硅区域部分地限定的深度，所述硅区域具有倾斜轮廓，使得 沟道区域的远侧区域具有比沟道区域的中间区域更深的深度。

公开(公告)号：US08338258B2

公开(公告)日：2012-12-25

申请号：US12625827

申请日：2009-11-25

申请人： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

发明人： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

IPC分类号： H01L21/336

CPC分类号： H01L29/1054 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78687

摘要： A method of fabricating an embedded stressor within a semiconductor structure and a semiconductor structure including the embedded stressor includes forming forming a dummy gate stack over a substrate of stressor material, anistropically etching sidewall portions of the substrate subjacent to the dummy gate stack to form the embedded stressor having angled sidewall portions, forming conductive material onto the angled sidewall portions of the embedded stressor, removing the dummy gate stack, planarizing the conductive material, and forming a gate stack on the conductive material.

摘要翻译： 一种在半导体结构内制造嵌入式应力器的方法以及包括所述嵌入式应力器的半导体结构的方法包括在所述应力源材料的衬底上形成形成虚拟栅极叠层的方法，将所述衬底的与所述虚拟栅极堆叠相邻的衬底的侧壁部分， 应力器具有成角度的侧壁部分，将导电材料形成在嵌入式应力源的成角度的侧壁部分上，去除虚拟栅极堆叠，平坦化导电材料，以及在导电材料上形成栅极叠层。

公开(公告)号：US20120261728A1

公开(公告)日：2012-10-18

申请号：US13529558

申请日：2012-06-21

申请人： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

发明人： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

IPC分类号： H01L29/78

CPC分类号： H01L29/1054 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78687

摘要： A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape.

摘要翻译： 半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; 设置在所述栅极堆叠的横向相对侧上的多个间隔件; 邻近间隔物的源极和漏极区域以及位于栅极堆叠下方并设置在源极和漏极区域之间的沟道区域; 以及位于所述沟道区域的下方并嵌入在所述半导体衬底内的应力器，所述嵌入式应力器由三角形形成。

公开(公告)号：US08354720B2

公开(公告)日：2013-01-15

申请号：US13529558

申请日：2012-06-21

申请人： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

发明人： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

IPC分类号： H01L27/12

CPC分类号： H01L29/1054 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78687

摘要： A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape.

摘要翻译： 半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; 设置在所述栅极堆叠的横向相对侧上的多个间隔件; 邻近间隔物的源极和漏极区域以及位于栅极堆叠下方并设置在源极和漏极区域之间的沟道区域; 以及位于所述沟道区域的下方并嵌入在所述半导体衬底内的应力器，所述嵌入式应力器由三角形形成。

公开(公告)号：US08304301B2

公开(公告)日：2012-11-06

申请号：US12621299

申请日：2009-11-18

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Ghavam G. Shahidi

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/66636 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer. Epitaxially growing the extremely thin semiconductor layer on the Ge layer ensures good thickness control across the wafer. This process could be used for SOI or bulk wafers.

摘要翻译： 公开了半导体器件和制造半导体器件的方法。 在一个实施例中，该方法包括提供半导体衬底，在衬底上外延生长Ge层，并在Ge层上外延生长半导体层，其中半导体层的厚度为10nm或更小。 该方法还包括去除Ge层的至少一部分以在Si层下形成空隙，并且至少部分地用电介质材料填充空隙。 以这种方式，半导体层成为非常薄的绝缘体上半导体层。 在一个实施例中，在空隙填充有电介质材料之后，在半导体层上生长原位掺杂的源极和漏极区。 在一个实施例中，该方法还包括退火所述源区和漏区以在半导体层中形成掺杂的延伸区。 在Ge层上外延生长极薄的半导体层确保跨晶片的良好的厚度控制。 该工艺可用于SOI或体晶片。

公开(公告)号：US20110121370A1

公开(公告)日：2011-05-26

申请号：US12625827

申请日：2009-11-25

申请人： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

发明人： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/1054 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78687

摘要： A method of fabricating an embedded stressor within a semiconductor structure and a semiconductor structure including the embedded stressor includes forming forming a dummy gate stack over a substrate of stressor material, anistropically etching sidewall portions of the substrate subjacent to the dummy gate stack to form the embedded stressor having angled sidewall portions, forming conductive material onto the angled sidewall portions of the embedded stressor, removing the dummy gate stack, planarizing the conductive material, and forming a gate stack on the conductive material.

摘要翻译： 一种在半导体结构内制造嵌入式应力器的方法以及包括所述嵌入式应力器的半导体结构的方法包括在所述应力源材料的衬底上形成形成虚拟栅极叠层的方法，将所述衬底的与所述虚拟栅极叠层相邻的衬底的侧壁部分， 应力器具有成角度的侧壁部分，将导电材料形成在嵌入式应力源的成角度的侧壁部分上，去除虚拟栅极堆叠，平坦化导电材料，以及在导电材料上形成栅极叠层。

公开(公告)号：US08710588B2

公开(公告)日：2014-04-29

申请号：US13595025

申请日：2012-08-27

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Ghavam G. Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L29/66636 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer.

摘要翻译： 公开了半导体器件和制造半导体器件的方法。 在一个实施例中，该方法包括提供半导体衬底，在衬底上外延生长Ge层，并在Ge层上外延生长半导体层，其中半导体层的厚度为10nm或更小。 该方法还包括去除Ge层的至少一部分以在Si层下形成空隙，并且至少部分地用电介质材料填充空隙。 以这种方式，半导体层成为非常薄的绝缘体上半导体层。 在一个实施例中，在空隙填充有电介质材料之后，在半导体层上生长原位掺杂的源极和漏极区。 在一个实施例中，该方法还包括退火所述源区和漏区以在半导体层中形成掺杂的延伸区。