公开(公告)号：US20050027975A1

公开(公告)日：2005-02-03

申请号：US10631055

申请日：2003-07-31

申请人： Scott Frommer ,  Balaram Sinharoy

发明人： Scott Frommer ,  Balaram Sinharoy

IPC分类号： G06F9/00 ,  G06F9/38

CPC分类号： G06F9/3863 ,  G06F9/3848

摘要： A method and system for recovering a global history vector. In the event of a non-branch flush, a tag may be received by a queue configured to store information about branch instructions. The queue may read a copy of the global history vector from an entry indexed by the tag. This copy may be inserted in a global history vector mechanism (“GHV mechanism”) configured to manage the global history vector. If the flush operation is a flush to a group of instructions that contains no branch instructions and the tag does not equal the next-to-write pointer in the queue, then the queue may transmit a command to the GHV mechanism to enter a mode where the GHV mechanism does not update the global history vector until the next branch instruction is fetched.

摘要翻译： 一种用于恢复全局历史向量的方法和系统。 在非分支刷新的情况下，标签可以被配置为存储关于分支指令的信息的队列接收。 队列可以从标签索引的条目读取全局历史向量的副本。 该副本可以被插入到被配置为管理全局历史向量的全局历史向量机制（“GHV机制”）中。 如果刷新操作与不包含分支指令的指令组齐平，并且该标签不等于队列中的写入后指针，则队列可以向GHV机制发送命令以进入模式，其中， 在获取下一个分支指令之前，GHV机制不会更新全局历史向量。

公开(公告)号：US20060184772A1

公开(公告)日：2006-08-17

申请号：US11055862

申请日：2005-02-11

申请人： Miles Dooley ,  Scott Frommer ,  Hung Le ,  Sheldon Levenstein ,  Anthony Saporito

发明人： Miles Dooley ,  Scott Frommer ,  Hung Le ,  Sheldon Levenstein ,  Anthony Saporito

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

摘要： A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the present invention comprises a data structure including information used by the processor. The data structure includes a group of bits to keep track of which instructions preceded a rejected instruction and therefore will be allowed to complete and which instructions follow the rejected instruction. The group of bits comprises a bit indicating whether a reject was a fast or slow reject; and a bit for each cycle that represents a state of an instruction passing through a pipeline. The processor speculatively continues to execute a set bit's corresponding instruction during stalled periods in order to generate addresses that will be needed when the stall period ends and normal dispatch resumes.

摘要翻译： 一种方法，系统和计算机程序产品，用于增强具有长档位的按顺序微处理器的性能。 特别地，本发明的机构提供了一种用于在处理器内存储数据的数据结构。 本发明的机构包括包括由处理器使用的信息的数据结构。 数据结构包括一组比特，用于跟踪被拒绝指令之前的哪些指令，因此将被允许完成，以及哪些指令遵循被拒绝的指令。 该比特组包括指示拒绝是否是快速或慢速拒绝的位; 以及表示通过管道的指令的状态的每个周期的一点。 处理器推测地在停滞时段期间继续执行设置位的相应指令，以便产生在停滞期结束并且恢复正常调度时将需要的地址。

公开(公告)号：US20060184739A1

公开(公告)日：2006-08-17

申请号：US11055818

申请日：2005-02-11

申请人： Scott Frommer ,  Sheldon Levenstein ,  Bruce Ronchetti ,  Anthony Saporito

发明人： Scott Frommer ,  Sheldon Levenstein ,  Bruce Ronchetti ,  Anthony Saporito

IPC分类号： G06F12/00

CPC分类号： G06F9/383 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861 ,  G06F12/0897

摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.

公开(公告)号：US20060179266A1

公开(公告)日：2006-08-10

申请号：US11054274

申请日：2005-02-09

申请人： Rachel Flood ,  Scott Frommer ,  David Hrusecky ,  Sheldon Levenstein ,  Michael Vaden

发明人： Rachel Flood ,  Scott Frommer ,  David Hrusecky ,  Sheldon Levenstein ,  Michael Vaden

IPC分类号： G06F12/00

CPC分类号： G06F9/355 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F12/1027

摘要： Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.

摘要翻译： 用于在数据处理系统中生成有效地址的方法，系统和计算机程序产品。 一种在数据处理系统中用于产生有效地址的方法包括通过计算有效地址的第一多个有效地址位来产生有效地址的第一部分，以及通过猜测有效地址产生有效地址的第二部分 多个有效地址的有效地址位。 通过智能地猜测形成有效地址的多个有效地址位，可以比在其中计算有效地址的所有有效地址位的系统中更快地生成有效地址并将其发送到转换单元。 该方法和系统特别适用于在多线程环境中的基于CAM的有效地址转换设计中生成有效地址。

公开(公告)号：US20060179258A1

公开(公告)日：2006-08-10

申请号：US11054262

申请日：2005-02-09

申请人： Miles Dooley ,  Scott Frommer ,  David Hrusecky ,  Sheldon Levenstein

发明人： Miles Dooley ,  Scott Frommer ,  David Hrusecky ,  Sheldon Levenstein

IPC分类号： G06F12/10

CPC分类号： G06F11/362

摘要： A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the critical area of the processor. The address comparison is split into two parts. The first part is a fast, partial address match comparator system. The second part is a slower, full address match comparator system. If a partial match between a requested address and a registry address is detected, then execution of the program or set of instructions requesting the address is temporarily suspended while a full address match check is performed. If the full address match check results in a full match between the requested address and a registry address, then the program or set of instructions is interrupted and stopped. Otherwise, the program or set of instructions continues execution.