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1.发明申请Silicide block isolated junction field effect transistor source, drain and gate 有权硅化物阻隔隔离结场效应晶体管源极，漏极和栅极公开(公告)号：US20080026515A1
公开(公告)日：2008-01-31
申请号：US11493229
申请日：2006-07-26
IPC分类号： H01L21/337
CPC分类号： H01L29/808 , H01L29/0642 , H01L29/66901
摘要： An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated with the JFET by suppressing the impact of surface states, among other things.
摘要翻译： 结型场效应晶体管（JFET）用形成栅极，源极和漏极区域的图案化硅化物块（SBLK）材料制成。 以这种方式利用硅化物块有助于通过抑制表面状态的影响来减少与JFET相关的低频（闪烁）噪声。
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2.发明授权Silicide block isolated junction field effect transistor source, drain and gate 有权硅化物阻隔隔离结场效应晶体管源极，漏极和栅极公开(公告)号：US07670890B2
公开(公告)日：2010-03-02
申请号：US11493229
申请日：2006-07-26
IPC分类号： H01L29/80 , H01L21/337
CPC分类号： H01L29/808 , H01L29/0642 , H01L29/66901
摘要： An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated with the JFET by suppressing the impact of surface states, among other things.
摘要翻译： 结型场效应晶体管（JFET）用形成栅极，源极和漏极区域的图案化硅化物块（SBLK）材料制成。 以这种方式利用硅化物块有助于通过抑制表面状态的影响来减少与JFET相关的低频（闪烁）噪声。
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公开(公告)号：US20100032804A1
公开(公告)日：2010-02-11
申请号：US12537246
申请日：2009-08-06
IPC分类号： H01L21/331 , H01L29/73
CPC分类号： H01L29/7378 , H01L21/76283 , H01L29/1004 , H01L29/161 , H01L29/66234 , H01L29/66242 , H01L29/732
摘要： High voltage bipolar transistors built with a BiCMOS process sequence exhibit reduced gain at high current densities due to the Kirk effect. Threshold current density for the onset of the Kirk effect is reduced by the lower doping density required for high voltage operation. The widened base region at high collector current densities due to the Kirk effect extends laterally into a region with a high density of recombination sites, resulting in an increase in base current and drop in the gain. The instant invention provides a bipolar transistor in an IC with an extended unsilicided base extrinsic region in a configuration that does not significantly increase a base-emitter capacitance. Lateral extension of the base extrinsic region may be accomplished using a silicide block layer, or an extended region of the emitter-base dielectric layer. A method of fabricating an IC with the inventive bipolar transistor is also disclosed.
摘要翻译： 由于Kirk效应，用BiCMOS工艺制造的高电压双极型晶体管在高电流密度下表现出减小的增益。 Kirk效应开始的阈值电流密度由于高电压操作所需的较低掺杂密度而降低。 由于Kirk效应，在高集电极电流密度下扩大的基极区域横向扩展到具有高密度复合位点的区域，导致基极电流增加和增益下降。 本发明在IC中提供了具有不显着增加基极 - 发射极电容的构造中的扩展的非硅化基极外部区域的双极晶体管。 可以使用硅化物阻挡层或发射极 - 基极介电层的延伸区域来实现基极外部区域的横向延伸。 还公开了利用本发明的双极晶体管制造IC的方法。
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公开(公告)号：US08847359B2
公开(公告)日：2014-09-30
申请号：US12537246
申请日：2009-08-06
IPC分类号： H01L21/331 , H01L29/73 , H01L29/66 , H01L21/762 , H01L29/737 , H01L29/732 , H01L29/161 , H01L29/10
CPC分类号： H01L29/7378 , H01L21/76283 , H01L29/1004 , H01L29/161 , H01L29/66234 , H01L29/66242 , H01L29/732
摘要： High voltage bipolar transistors built with a BiCMOS process sequence exhibit reduced gain at high current densities due to the Kirk effect. Threshold current density for the onset of the Kirk effect is reduced by the lower doping density required for high voltage operation. The widened base region at high collector current densities due to the Kirk effect extends laterally into a region with a high density of recombination sites, resulting in an increase in base current and drop in the gain. The instant invention provides a bipolar transistor in an IC with an extended unsilicided base extrinsic region in a configuration that does not significantly increase a base-emitter capacitance. Lateral extension of the base extrinsic region may be accomplished using a silicide block layer, or an extended region of the emitter-base dielectric layer. A method of fabricating an IC with the inventive bipolar transistor is also disclosed.
摘要翻译： 由于Kirk效应，用BiCMOS工艺制造的高电压双极型晶体管在高电流密度下表现出减小的增益。 Kirk效应开始的阈值电流密度由于高电压操作所需的较低掺杂密度而降低。 由于Kirk效应，在高集电极电流密度下扩大的基极区域横向扩展到具有高密度复合位点的区域，导致基极电流增加和增益下降。 本发明在IC中提供了具有不显着增加基极 - 发射极电容的构造中的扩展的非硅化基极外部区域的双极晶体管。 可以使用硅化物阻挡层或发射极 - 基极介电层的延伸区域来实现基极外部区域的横向延伸。 还公开了利用本发明的双极晶体管制造IC的方法。
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5.发明授权Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection 有权具有栅极自保护的集成电路的制造方法和具有栅极自保护的集成电路公开(公告)号：US07772057B2
公开(公告)日：2010-08-10
申请号：US11470760
申请日：2006-09-07
IPC分类号： H01L21/337
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/0251 , H01L27/0705
摘要： An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.
摘要翻译： 具有栅极自保护的集成电路包括MOS器件和双极器件，其中所述集成电路还包括具有电活性区域的半导体层，在其上形成MOS器件和双极器件，并且在其上形成用于隔离的电无活性区域 电活性区域彼此。 MOS器件包括栅极结构和体接触结构，其中所述体接触结构由沉积在所述半导体层的电活性区域上的选定区域中的基底层形成，并且所述体接触结构与所述栅极电连接 结构体。 形成身体接触结构的基层也形成双极器件的基部。 本发明还涉及一种用于制造这种集成电路的方法。
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6.发明授权Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection 有权具有栅极自保护的集成电路的制造方法和具有栅极自保护的集成电路公开(公告)号：US08294218B2
公开(公告)日：2012-10-23
申请号：US12796386
申请日：2010-06-08
IPC分类号： H01L27/06
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/0251 , H01L27/0705
摘要： An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.
摘要翻译： 具有栅极自保护的集成电路包括MOS器件和双极器件，其中所述集成电路还包括具有电活性区域的半导体层，在其上形成MOS器件和双极器件，并且在其上形成用于隔离的电无活性区域 电活性区域彼此。 MOS器件包括栅极结构和体接触结构，其中所述体接触结构由沉积在所述半导体层的电活性区域上的选定区域中的基底层形成，并且所述体接触结构与所述栅极电连接 结构体。 形成身体接触结构的基层也形成双极器件的基部。 本发明还涉及一种用于制造这种集成电路的方法。
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公开(公告)号：US07312119B2
公开(公告)日：2007-12-25
申请号：US11549248
申请日：2006-10-13
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/40 , H01L27/0629 , H01L27/0805
摘要： The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a lower gate-oxide dielectric (26) arranged between the base plate (16) and the center plate (32), a cover plate (36) made of a metallic conductor and arranged above the center plate (32), and an upper dielectric (34) arranged between the center plate (32) and the cover plate (36). The cover plate (36) and the base plate (16) are electrically connected to each other and together form a first capacitor electrode. The center plate (32) forms a second capacitor electrode. The invention further relates to an integrated circuit with such a stacked capacitor, as well as to a method for fabrication of a stacked capacitor as part of a CMOS process.
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