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    Method and apparatus for calibration of stray capacitance mismatch in a closed loop electro-mechanical accelerometer
    1.
    发明授权
    Method and apparatus for calibration of stray capacitance mismatch in a closed loop electro-mechanical accelerometer 有权
    用于校准闭环机电加速度计中杂散电容失配的方法和装置

    公开(公告)号：US6035694A

    公开(公告)日：2000-03-14

    申请号：US268072

    申请日：1999-03-12

    申请人： Scott T. Dupuie ,  Richard A. Johnson ,  Ben W. Jones ,  Mauricio A. Zavaleta ,  Mark E. Burchfield ,  Burton A. Devolk ,  Franklin W. Mayo ,  Michael L. Abrams ,  Roger Maher

    发明人： Scott T. Dupuie ,  Richard A. Johnson ,  Ben W. Jones ,  Mauricio A. Zavaleta ,  Mark E. Burchfield ,  Burton A. Devolk ,  Franklin W. Mayo ,  Michael L. Abrams ,  Roger Maher

    IPC分类号： G01P15/125 ,  G01P15/13 ,  G01P21/00 ,  G01P15/00

    CPC分类号： G01P21/00 ,  G01P15/125 ,  G01P15/131

    摘要： A method and apparatus for measuring and compensating for stray capacitance of a micro-machined sensor of an accelerometer system is disclosed. Stray capacitance differences between a top plate and a sensing element and between a bottom plate and the sensing element degrade accelerometer performance if not compensated for. Measurement of stray capacitance difference is achieved by operating the accelerometer in two calibration phases and measuring the steady-state output voltage in each of the two phases. In calibration phase 1, no force is applied to the sensor during clock intervals 1-4. In calibration phase 2, a dummy force up is applied and then a dummy force down is applied during those intervals 1-4. The difference in the output voltage of the two calibration phases is representative of the difference in stray capacitance of the sensor. Capacitance is added to the top or bottom plates in an amount proportional to the measured stray capacitance. The procedure is repeated until the voltage difference of the two calibration phases is zeroed, which is indicative that the inherent stray capacitance has been zeroed.

    摘要翻译： 公开了一种用于测量和补偿加速度计系统的微加工传感器的杂散电容的方法和装置。 顶板和感测元件之间以及底板和感测元件之间的杂散电容差会降低加速度计的性能，如果没有得到补偿。 通过在两个校准阶段中操作加速度计并测量两相中的每一个的稳态输出电压来实现杂散电容差的测量。 在校准阶段1中，在时钟间隔1-4期间，传感器不会施加力。 在校准阶段2中，施加虚拟加力，然后在这些间隔1-4期间施加虚拟力。 两个校准相位的输出电压的差异代表传感器杂散电容的差异。 将电容以与测量的杂散电容成比例的量加到顶板或底板上。 重复该过程，直到两个校准相的电压差为零，这表明固有杂散电容已被归零。

    Method and apparatus for generation of test bitstreams and testing of closed loop transducers
    2.
    发明授权
    Method and apparatus for generation of test bitstreams and testing of closed loop transducers 有权
    用于产生测试比特流和闭环换能器测试的方法和装置

    公开(公告)号：US6023960A

    公开(公告)日：2000-02-15

    申请号：US304421

    申请日：1999-04-28

    申请人： Michael L. Abrams ,  Ben W. Jones ,  Franklin W. Mayo ,  Scott T. Dupuie ,  Jeffery C. Gannon ,  Richard A. Johnson

    发明人： Michael L. Abrams ,  Ben W. Jones ,  Franklin W. Mayo ,  Scott T. Dupuie ,  Jeffery C. Gannon ,  Richard A. Johnson

    IPC分类号： G01P21/00 ,  G01C17/38

    CPC分类号： G01P21/00

    摘要： A high performance method and apparatus for testing a closed loop transducer is disclosed. A test bitstream signal is combined with a .SIGMA..DELTA. feedback bitstream of the transducer to produce a combined bitstream which is converted to a physical feedback to the sensor of the transducer. The .SIGMA..DELTA. bitstream output of the transducer is recorded for later analysis so as to test characteristics of the transducer. The test bitstream signal is preferably an oversampled, pulse density modulated signal. A testing arrangement is provided which is based upon the storage of short-length test patterns which are repetitively accessed to form a continuous test pattern. The test bitstream provided by the method of the invention produces very low noise and low distortion test signals where a repetitive test pattern is equivalent in length to one period of the test signal.

    摘要翻译： 公开了一种用于测试闭环换能器的高性能方法和装置。 测试比特流信号与换能器的SIGMA DELTA反馈比特流组合以产生被转换成对换能器的传感器的物理反馈的组合比特流。 记录换能器的SIGMA DELTA比特流输出用于后续分析，以便测试换能器的特性。 测试比特流信号优选地是过采样的脉冲密度调制信号。 提供了一种测试装置，其基于重复访问的短长度测试图案的存储，以形成连续的测试图案。 通过本发明的方法提供的测试比特流产生非常低的噪声和低失真测试信号，其中重复测试模式长度与测试信号的一个周期相等。

    Method and apparatus for generation of test bitstreams and testing of close loop transducers
    3.
    发明授权
    Method and apparatus for generation of test bitstreams and testing of close loop transducers 失效
    用于产生测试比特流的方法和装置以及闭环换能器的测试

    公开(公告)号：US6101864A

    公开(公告)日：2000-08-15

    申请号：US992663

    申请日：1997-12-17

    申请人： Michael L. Abrams ,  Ben W. Jones ,  Franklin W. Mayo ,  Scott T. Dupuie ,  Jeffery C. Gannon ,  Richard A. Johnson

    发明人： Michael L. Abrams ,  Ben W. Jones ,  Franklin W. Mayo ,  Scott T. Dupuie ,  Jeffery C. Gannon ,  Richard A. Johnson

    IPC分类号： G01P21/00 ,  G01C17/38

    CPC分类号： G01P21/00

    摘要： A high performance method and apparatus for testing a closed loop transducer is disclosed. A test bitstream signal is combined with a .SIGMA..DELTA. feedback bitstream of the transducer to produce a combined bitstream which is converted to a physical feedback to the sensor of the transducer. The .SIGMA..DELTA. bitstream output of the transducer is recorded for later analysis so as to test characteristics of the transducer. The test bitstream signal is preferably an oversampled, pulse density modulated signal. A testing arrangement is provided which is based upon the storage of short-length test patterns which are repetitively accessed to form a continuous test pattern. The test bitstream provided by the method of the invention produces very low noise and low distortion test signals where a repetitive test pattern is equivalent in length to one period of the test signal.

    摘要翻译： 公开了一种用于测试闭环换能器的高性能方法和装置。 测试比特流信号与换能器的SIGMA DELTA反馈比特流组合以产生被转换成对换能器的传感器的物理反馈的组合比特流。 记录换能器的SIGMA DELTA比特流输出用于后续分析，以便测试换能器的特性。 测试比特流信号优选地是过采样的脉冲密度调制信号。 提供了一种测试装置，其基于重复访问的短长度测试图案的存储，以形成连续的测试图案。 通过本发明的方法提供的测试比特流产生非常低的噪声和低失真测试信号，其中重复测试模式长度与测试信号的一个周期相等。