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    Method and apparatus for generation of test bitstreams and testing of closed loop transducers
    1.
    发明授权
    Method and apparatus for generation of test bitstreams and testing of closed loop transducers 有权
    用于产生测试比特流和闭环换能器测试的方法和装置

    公开(公告)号：US6023960A

    公开(公告)日：2000-02-15

    申请号：US304421

    申请日：1999-04-28

    申请人： Michael L. Abrams ,  Ben W. Jones ,  Franklin W. Mayo ,  Scott T. Dupuie ,  Jeffery C. Gannon ,  Richard A. Johnson

    发明人： Michael L. Abrams ,  Ben W. Jones ,  Franklin W. Mayo ,  Scott T. Dupuie ,  Jeffery C. Gannon ,  Richard A. Johnson

    IPC分类号： G01P21/00 ,  G01C17/38

    CPC分类号： G01P21/00

    摘要： A high performance method and apparatus for testing a closed loop transducer is disclosed. A test bitstream signal is combined with a .SIGMA..DELTA. feedback bitstream of the transducer to produce a combined bitstream which is converted to a physical feedback to the sensor of the transducer. The .SIGMA..DELTA. bitstream output of the transducer is recorded for later analysis so as to test characteristics of the transducer. The test bitstream signal is preferably an oversampled, pulse density modulated signal. A testing arrangement is provided which is based upon the storage of short-length test patterns which are repetitively accessed to form a continuous test pattern. The test bitstream provided by the method of the invention produces very low noise and low distortion test signals where a repetitive test pattern is equivalent in length to one period of the test signal.

    摘要翻译： 公开了一种用于测试闭环换能器的高性能方法和装置。 测试比特流信号与换能器的SIGMA DELTA反馈比特流组合以产生被转换成对换能器的传感器的物理反馈的组合比特流。 记录换能器的SIGMA DELTA比特流输出用于后续分析，以便测试换能器的特性。 测试比特流信号优选地是过采样的脉冲密度调制信号。 提供了一种测试装置，其基于重复访问的短长度测试图案的存储，以形成连续的测试图案。 通过本发明的方法提供的测试比特流产生非常低的噪声和低失真测试信号，其中重复测试模式长度与测试信号的一个周期相等。

    Method and apparatus for generation of test bitstreams and testing of close loop transducers
    2.
    发明授权
    Method and apparatus for generation of test bitstreams and testing of close loop transducers 失效
    用于产生测试比特流的方法和装置以及闭环换能器的测试

    公开(公告)号：US6101864A

    公开(公告)日：2000-08-15

    申请号：US992663

    申请日：1997-12-17

    申请人： Michael L. Abrams ,  Ben W. Jones ,  Franklin W. Mayo ,  Scott T. Dupuie ,  Jeffery C. Gannon ,  Richard A. Johnson

    发明人： Michael L. Abrams ,  Ben W. Jones ,  Franklin W. Mayo ,  Scott T. Dupuie ,  Jeffery C. Gannon ,  Richard A. Johnson

    IPC分类号： G01P21/00 ,  G01C17/38

    CPC分类号： G01P21/00

    摘要： A high performance method and apparatus for testing a closed loop transducer is disclosed. A test bitstream signal is combined with a .SIGMA..DELTA. feedback bitstream of the transducer to produce a combined bitstream which is converted to a physical feedback to the sensor of the transducer. The .SIGMA..DELTA. bitstream output of the transducer is recorded for later analysis so as to test characteristics of the transducer. The test bitstream signal is preferably an oversampled, pulse density modulated signal. A testing arrangement is provided which is based upon the storage of short-length test patterns which are repetitively accessed to form a continuous test pattern. The test bitstream provided by the method of the invention produces very low noise and low distortion test signals where a repetitive test pattern is equivalent in length to one period of the test signal.

    摘要翻译： 公开了一种用于测试闭环换能器的高性能方法和装置。 测试比特流信号与换能器的SIGMA DELTA反馈比特流组合以产生被转换成对换能器的传感器的物理反馈的组合比特流。 记录换能器的SIGMA DELTA比特流输出用于后续分析，以便测试换能器的特性。 测试比特流信号优选地是过采样的脉冲密度调制信号。 提供了一种测试装置，其基于重复访问的短长度测试图案的存储，以形成连续的测试图案。 通过本发明的方法提供的测试比特流产生非常低的噪声和低失真测试信号，其中重复测试模式长度与测试信号的一个周期相等。

    Method and apparatus for calibration of stray capacitance mismatch in a closed loop electro-mechanical accelerometer
    3.
    发明授权
    Method and apparatus for calibration of stray capacitance mismatch in a closed loop electro-mechanical accelerometer 有权
    用于校准闭环机电加速度计中杂散电容失配的方法和装置

    公开(公告)号：US6035694A

    公开(公告)日：2000-03-14

    申请号：US268072

    申请日：1999-03-12

    申请人： Scott T. Dupuie ,  Richard A. Johnson ,  Ben W. Jones ,  Mauricio A. Zavaleta ,  Mark E. Burchfield ,  Burton A. Devolk ,  Franklin W. Mayo ,  Michael L. Abrams ,  Roger Maher

    发明人： Scott T. Dupuie ,  Richard A. Johnson ,  Ben W. Jones ,  Mauricio A. Zavaleta ,  Mark E. Burchfield ,  Burton A. Devolk ,  Franklin W. Mayo ,  Michael L. Abrams ,  Roger Maher

    IPC分类号： G01P15/125 ,  G01P15/13 ,  G01P21/00 ,  G01P15/00

    CPC分类号： G01P21/00 ,  G01P15/125 ,  G01P15/131

    摘要： A method and apparatus for measuring and compensating for stray capacitance of a micro-machined sensor of an accelerometer system is disclosed. Stray capacitance differences between a top plate and a sensing element and between a bottom plate and the sensing element degrade accelerometer performance if not compensated for. Measurement of stray capacitance difference is achieved by operating the accelerometer in two calibration phases and measuring the steady-state output voltage in each of the two phases. In calibration phase 1, no force is applied to the sensor during clock intervals 1-4. In calibration phase 2, a dummy force up is applied and then a dummy force down is applied during those intervals 1-4. The difference in the output voltage of the two calibration phases is representative of the difference in stray capacitance of the sensor. Capacitance is added to the top or bottom plates in an amount proportional to the measured stray capacitance. The procedure is repeated until the voltage difference of the two calibration phases is zeroed, which is indicative that the inherent stray capacitance has been zeroed.

    摘要翻译： 公开了一种用于测量和补偿加速度计系统的微加工传感器的杂散电容的方法和装置。 顶板和感测元件之间以及底板和感测元件之间的杂散电容差会降低加速度计的性能，如果没有得到补偿。 通过在两个校准阶段中操作加速度计并测量两相中的每一个的稳态输出电压来实现杂散电容差的测量。 在校准阶段1中，在时钟间隔1-4期间，传感器不会施加力。 在校准阶段2中，施加虚拟加力，然后在这些间隔1-4期间施加虚拟力。 两个校准相位的输出电压的差异代表传感器杂散电容的差异。 将电容以与测量的杂散电容成比例的量加到顶板或底板上。 重复该过程，直到两个校准相的电压差为零，这表明固有杂散电容已被归零。

    Television receiver suitable for multi-standard operation and method therefor
    5.
    发明授权
    Television receiver suitable for multi-standard operation and method therefor 有权
    适用于多标准操作的电视接收机及其方法

    公开(公告)号：US07675996B2

    公开(公告)日：2010-03-09

    申请号：US11194034

    申请日：2005-07-29

    申请人： Richard A. Johnson ,  James M. Nohrden ,  Scott T. Dupuie ,  Andrew W. Dornbusch

    发明人： Richard A. Johnson ,  James M. Nohrden ,  Scott T. Dupuie ,  Andrew W. Dornbusch

    IPC分类号： H03K9/00 ,  H04L27/00

    CPC分类号： H03J1/0008 ,  H03D7/00 ,  H04B1/0007 ,  H04B1/28 ,  H04B15/04 ,  H04B2215/064 ,  H04B2215/065 ,  H04N5/4446 ,  H04N5/46 ,  H04N21/4263 ,  H04N21/4305

    摘要： A receiver (1100) includes a direct digital frequency synthesizer (130), a mixer (105), and a clock source (1110, 1130). The direct digital frequency synthesizer has an input terminal for receiving a first clock signal at a first frequency, and an output terminal for providing a digital local oscillator signal synchronously with the first clock signal. The mixer (105) has a first input terminal for receiving a radio frequency (RF) signal, a second input terminal coupled to the output terminal of the direct digital frequency synthesizer (130), and an output terminal for providing an IF signal having a spectrum centered about a selectable one of a plurality of center frequencies. The clock source (1110, 1130) has an output terminal for providing the first clock signal without using a harmonic frequency that overlaps the spectrum for the plurality of center frequencies.

    摘要翻译： 接收器（1100）包括直接数字频率合成器（130），混频器（105）和时钟源（1110,1130）。 直接数字频率合成器具有用于以第一频率接收第一时钟信号的输入端子和用于与第一时钟信号同步地提供数字本地振荡器信号的输出端子。 混频器（105）具有用于接收射频（RF）信号的第一输入端，耦合到直接数字频率合成器（130）的输出端的第二输入端，以及用于提供IF信号的输出端， 频谱以多个中心频率中的可选择的一个为中心。 时钟源（1110,1130）具有用于提供第一时钟信号的输出端，而不使用与多个中心频率的频谱重叠的谐波频率。

    MIXING DAC AND POLYPHASE FILTER ARCHITECTURES FOR A RADIO FREQUENCY RECEIVER
    6.
    发明申请
    MIXING DAC AND POLYPHASE FILTER ARCHITECTURES FOR A RADIO FREQUENCY RECEIVER 审中-公开
    无线电频率接收机的混合DAC和多相滤波器架构

    公开(公告)号：US20080132189A1

    公开(公告)日：2008-06-05

    申请号：US11565481

    申请日：2006-11-30

    申请人： Adrian Maxim ,  Matthew Powell ,  Scott T. Dupuie ,  Richard A. Johnson

    发明人： Adrian Maxim ,  Matthew Powell ,  Scott T. Dupuie ,  Richard A. Johnson

    IPC分类号： H04B1/18

    CPC分类号： H04B1/28

    摘要： A receiver (200) includes a mixing digital-to-analog converter (DAC) (208), a direct digital frequency synthesizer (DDFS), a transimpedance amplifier (TIA) (204) and a first polyphase filter (PPF) (202). The mixing DAC (208) includes a radio frequency (RF) transconductance section for providing an RF current signal responsive to an RF signal and a switching section. The switching section is coupled to the RF transconductance section and includes inputs for receiving bits associated with a digital local oscillator (LO) signal. The switching section is configured to mix the RF current signal with the digital LO signal to provide an analog output signal at outputs of the switching section. The transimpedance amplifier (TIA) (204) includes inputs each coupled to a respective one of the outputs of the switching section and outputs. The first PPF (202) includes inputs each coupled to a respective one the outputs of the TIA (204).

    摘要翻译： 接收器（200）包括混合数模转换器（DAC）（208），直接数字频率合成器（DDFS），跨阻抗放大器（TIA）（204）和第一多相滤波器（PPF） 。 混合DAC（208）包括射频（RF）跨导部分，用于响应于RF信号和切换部分提供RF电流信号。 开关部分耦合到RF跨导部分，并且包括用于接收与数字本地振荡器（LO）信号相关联的位的输入。 开关部分被配置为将RF电流信号与数字LO信号混合，以在开关部分的输出处提供模拟输出信号。 跨阻放大器（TIA）（204）包括各自耦合到开关部分的相应输出端和输出端的输入端。 第一PPF（202）包括各自与TIA（204）的输出相连接的输入。

    Telephone line interface for DAA circuitry
    7.
    发明授权
    Telephone line interface for DAA circuitry 失效
    DAA电路的电话线接口

    公开(公告)号：US07218713B1

    公开(公告)日：2007-05-15

    申请号：US10414442

    申请日：2003-04-15

    申请人： Scott T. Dupuie

    发明人： Scott T. Dupuie

    IPC分类号： H04M1/56 ,  H04M15/06 ,  H04M1/00 ,  H04M9/00

    CPC分类号： H04M1/738

    摘要： A telephone line interface and associated circuitry that may be implemented to simultaneously couple DC loop voltage, ring bursts, and caller-ID data to the phone line side of a DAA circuit through a single two wire resistively coupled interface. The interface and circuitry may be implemented to combine processing of the DC loop voltage and ring bursts into a single circuit, with processing of caller-ID data being performed separately.

    摘要翻译： 电话线接口和相关联的电路，其可被实现为通过单个二线电阻耦合接口将DC回路电压，环形突发和呼叫者ID数据同时耦合到DAA电路的电话线侧。 可以实现接口和电路以将DC环路电压和环形突发的处理组合成单个电路，并且单独执行呼叫者ID数据的处理。

    Multi-stage variable gain amplifier utilizing overlapping gain curves to compensate for log-linear errors
    8.
    发明授权
    Multi-stage variable gain amplifier utilizing overlapping gain curves to compensate for log-linear errors 有权
    利用重叠增益曲线补偿对数线性误差的多级可变增益放大器

    公开(公告)号：US07098732B2

    公开(公告)日：2006-08-29

    申请号：US10954969

    申请日：2004-09-30

    申请人： Scott T. Dupuie

    发明人： Scott T. Dupuie

    IPC分类号： H03G5/16

    CPC分类号： H03G7/06

    摘要： A multi-stage variable gain amplifier is disclosed that utilizes overlapping gain curves to compensate for log-linear errors. Each gain stage is configured to approximate a log-linear response with a sinusoidal error term such that a portion of the curve has positive errors and a portion of the curve has negative errors. In operation, the control signal inputs for the gain stages are driven such that the gain curves overlap and positive errors in each stage are offset by negative errors in the adjacent stage. The resulting combined gain is a more log-linear response.

    摘要翻译： 公开了一种利用重叠增益曲线来补偿对数线性误差的多级可变增益放大器。 每个增益级配置为用正弦误差项近似对数线性响应，使得曲线的一部分具有正误差，并且一部分曲线具有负误差。 在操作中，用于增益级的控制信号输入被驱动，使得增益曲线重叠，并且每个级中的正误差被相邻级中的负误差抵消。 所得到的组合增益是更对数线性响应。

    Automatic voltage reference scaling in analog-to-digital and digital-to-analog converters
    9.
    发明授权
    Automatic voltage reference scaling in analog-to-digital and digital-to-analog converters 失效
    模数转换器和数模转换器中的自动电压参考比例

    公开(公告)号：US6091350A

    公开(公告)日：2000-07-18

    申请号：US678608

    申请日：1996-07-15

    申请人： John J. Paulos ,  Scott T. Dupuie

    发明人： John J. Paulos ,  Scott T. Dupuie

    IPC分类号： H03M1/34 ,  H03M1/74 ,  H03M3/02 ,  H03M1/00

    CPC分类号： H03M3/392 ,  H03M3/458 ,  H03M3/50

    摘要： Analog-to-digital and digital-to-analog converters are described which have internal reference voltage generators. These voltage generators include circuitry which senses the magnitude of the power supply voltage applied to the chip. The internal reference voltage generators then select one of two internal reference voltages as a reference voltage for the conversion operations depending on the magnitude of the power supply voltage.

    摘要翻译： 描述了具有内部参考电压发生器的模数转换器和数模转换器。 这些电压发生器包括检测施加到芯片的电源电压的大小的电路。 内部参考电压发生器随后根据电源电压的大小选择两个内部参考电压之一作为转换操作的参考电压。