公开(公告)号：US07936854B2

公开(公告)日：2011-05-03

申请号：US12103622

申请日：2008-04-15

申请人： Sean Foley ,  Cazel Lombaard ,  Tony Blake ,  Paul Scott ,  Mohamed Sardi

发明人： Sean Foley ,  Cazel Lombaard ,  Tony Blake ,  Paul Scott ,  Mohamed Sardi

IPC分类号： H04L7/00

CPC分类号： H04J3/0685 ,  H04J3/047

摘要： A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit slip that results in the moving of a character frame in the recovered data of a deserializer. According to one embodiment of the invention, the moving of the character frame is prompted by a single control signal of a clock divider circuit which causes the removal of a single clock cycle of a clock signal supplied to said deserializer.

摘要翻译： 公开了一种循环滑移框架的方法和系统。 该方法包括接收异步信号并在接收到异步信号之后产生同步脉冲。 该方法还提供了同步脉冲用于影响导致在解串器的恢复数据中移动字符帧的位滑动。 根据本发明的一个实施例，字符帧的移动由时钟分频器电路的单个控制信号提示，其导致去除提供给所述解串器的时钟信号的单个时钟周期。

公开(公告)号：US20080192871A1

公开(公告)日：2008-08-14

申请号：US12103622

申请日：2008-04-15

申请人： Sean Foley ,  Cazel Lombaard ,  Tony Blake ,  Paul Scott ,  Mohamed Sardi

发明人： Sean Foley ,  Cazel Lombaard ,  Tony Blake ,  Paul Scott ,  Mohamed Sardi

IPC分类号： H04L7/00

CPC分类号： H04J3/0685 ,  H04J3/047

摘要： A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit slip that results in the moving of a character frame in the recovered data of a deserializer. According to one embodiment of the invention, the moving of the character frame is prompted by a single control signal of a clock divider circuit which causes the removal of a single clock cycle of a clock signal supplied to said deserializer.

摘要翻译： 公开了一种循环滑移框架的方法和系统。 该方法包括接收异步信号并在接收到异步信号之后产生同步脉冲。 该方法还提供了同步脉冲用于影响导致在解串器的恢复数据中移动字符帧的位滑动。 根据本发明的一个实施例，字符帧的移动由时钟分频器电路的单个控制信号提示，其导致去除提供给所述解串器的时钟信号的单个时钟周期。

公开(公告)号：US07372928B1

公开(公告)日：2008-05-13

申请号：US10295736

申请日：2002-11-15

申请人： Sean Foley ,  Carel Lombaard ,  Tony Blake ,  Paul Scott ,  Mohamed Sardi

发明人： Sean Foley ,  Carel Lombaard ,  Tony Blake ,  Paul Scott ,  Mohamed Sardi

IPC分类号： H04L7/00

CPC分类号： H04J3/0685 ,  H04J3/047

摘要： A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit slip that results in the moving of a character frame in the recovered data of a deserializer. According to one embodiment of the invention, the moving of the character frame is prompted by a single control signal of a clock divider circuit which causes the removal of a single clock cycle of a clock signal supplied to said deserializer.

摘要翻译： 公开了一种循环滑移框架的方法和系统。 该方法包括接收异步信号并在接收到异步信号之后产生同步脉冲。 该方法还提供了同步脉冲用于影响导致在解串器的恢复数据中移动字符帧的位滑动。 根据本发明的一个实施例，字符帧的移动由时钟分频器电路的单个控制信号提示，其导致去除提供给所述解串器的时钟信号的单个时钟周期。

公开(公告)号：US06970115B1

公开(公告)日：2005-11-29

申请号：US10876985

申请日：2004-06-25

申请人： Mohamed Sardi ,  Paul Scott ,  Sean Foley

发明人： Mohamed Sardi ,  Paul Scott ,  Sean Foley

IPC分类号： H03M9/00 ,  H04J3/04 ,  H04J3/06 ,  H04J3/07 ,  H04L7/00

CPC分类号： H03M9/00 ,  H04J3/047 ,  H04J3/0602 ,  H04J3/0685

摘要： A system and method are provided for synchronizing a frame of related bits output from a deserializer to the related bits serially fed to the deserializer. Synchronization is achieved by overcoming a slip bit problem by selectively increasing the frame clock cycle during times in which the slip bit occurs. The deserializer is controlled by a clock generator that can include a counter which generates the frame clock. The counter can be asynchronously or synchronously reset, without any glitches occurring within the deserializer and, thus, avoiding any invalid bits output from the deserializer. The asynchronous reset forces the counter to a deterministic state, and the synchronous reset sets the counter to a valid state. In each instance, however, resets do not impart glitches to the deserializer and the deserializer output frame is maintained synchronous to related bits serially fed to the deserializer.

摘要翻译： 提供了一种系统和方法，用于将从解串器输出的相关位的帧同步到串行馈送到解串器的相关位。 通过在发生滑移位的时间期间选择性地增加帧时钟周期来克服滑点问题来实现同步。 解串器由时钟发生器控制，时钟发生器可以包括产生帧时钟的计数器。 计数器可以异步或同步复位，而不会在解串器内发生任何毛刺，从而避免从解串器输出的任何无效位。 异步复位将计数器强制为确定性状态，同步复位将计数器设置为有效状态。 然而，在每一种情况下，复位不会给解串器发出毛刺，并且解串器输出帧与串行馈送到解串器的相关位保持同步。

公开(公告)号：US07409616B1

公开(公告)日：2008-08-05

申请号：US10876990

申请日：2004-06-25

申请人： Mohamed Sardi ,  Paul Scott

发明人： Mohamed Sardi ,  Paul Scott

IPC分类号： G01R31/28

CPC分类号： G01R31/31715

摘要： A system and method are provided for built-in-self test of any bits that have slipped from their appropriate positions within a frame character clock cycle. If a bit has slipped, then the built-in-self test mechanism can also implement either a clock generation stretch operation or a barrel shift operation to readjust the frame boundary output from a receiver with a 1-to-N deserializer. A pseudo-random bit sequence can be generated having the same logic value in both the receiver and transmitter, where the output of the deserializer which receives the transmitted bits is compared bit-by-bit with the receiver-generated bits as part of the built-in-self test mechanism. If a bit is determined to have been slipped, then error correction occurs with aliasing and phase jitter in mind.

摘要翻译： 提供了一种系统和方法，用于对在帧字符时钟周期内从其适当位置滑落的任何位进行内置自检。 如果有一点滑动，那么内置的自检机构也可以实现时钟产生拉伸操作或桶形移位操作，以使用1对N解串器重新调整从接收器输出的帧边界。 可以生成在接收机和发射机中具有相同逻辑值的伪随机比特序列，其中接收所发送的比特的解串器的输出与接收机生成的比特逐位比较，作为构建的一部分 自我测试机制。 如果确定有一点被滑动，则会出现混叠和相位抖动的错误纠正。

公开(公告)号：US07069458B1

公开(公告)日：2006-06-27

申请号：US10222129

申请日：2002-08-16

申请人： Mohamed Sardi ,  Gabriel M. Li

发明人： Mohamed Sardi ,  Gabriel M. Li

IPC分类号： G06F13/42

CPC分类号： H04L7/0338 ,  H03L7/0996

摘要： A parallel data interface and method is provided herein, which adjusts a timing relationship of a clock signal to not only minimize clock skew, but to also compensate for noise components that may affect one or more paths of a parallel data bus. In some embodiments, the parallel data interface includes a first phase generator coupled to generate a first plurality of time delay pulses, and a first phase selector adapted to select one of the first plurality of time delay pulses to adjust the timing of a clock signal to sample each and every one of the plurality of data signals between minimum setup and hold time thresholds. In some embodiments, the parallel data interface includes a second phase generator coupled to generate a second plurality of time delay pulses, and a second phase selector adapted to select one of the second plurality of time delay pulses to adjust the timing of the clock signal to output the plurality of data signals from the data interface at least an amount of time (i.e., an access time) after the adjusted clock transition is output from the data interface.

摘要翻译： 本文提供并行数据接口和方法，其调整时钟信号的定时关系，以便不仅最小化时钟偏差，而且还补偿可能影响并行数据总线的一个或多个路径的噪声分量。 在一些实施例中，并行数据接口包括耦合以产生第一多个时间延迟脉冲的第一相位发生器，以及适于选择第一多个时间延迟脉冲之一以调整时钟信号定时的第一相位选择器 在最小建立和保持时间阈值之间对多个数据信号中的每一个进行采样。 在一些实施例中，并行数据接口包括耦合以产生第二多个时间延迟脉冲的第二相位发生器，以及适于选择第二多个时间延迟脉冲之一以调整时钟信号定时的第二相位选择器 在从数据接口输出调整后的时钟转移之后，从数据接口输出多个数据信号至少一段时间（即访问时间）。