摘要:
An equalizer coefficients generator receives a DSS sequence and a DSS readback sequence, which is a function of a channel processing of the DSS sequence by a read channel. The generator generates a coefficient cyclic equalizer vector as a function of the DSS sequence and the DSS readback sequence. The generator further generates an error signal as a function of a comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector. An unacceptable error signal indicates a need to adjust the coefficient cyclic equalizer vector to yield an acceptable comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector.
摘要:
An equalizer coefficients generator receives a DSS sequence and a DSS readback sequence, which is a function of a channel processing of the DSS sequence by a read channel. The generator generates a coefficient cyclic equalizer vector as a function of the DSS sequence and the DSS readback sequence. The generator further generates an error signal as a function of a comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector. An unacceptable error signal indicates a need to adjust the coefficient cyclic equalizer vector to yield an acceptable comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector.
摘要:
Provided is a method for receiving a DSS sequence and a DSS readback sequence, which is a function of a channel processing of the DSS sequence by a read channel. A coefficient cyclic equalizer vector is generated as a function of the DSS sequence and the DSS readback sequence. An error signal is generated as a function of a comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector. An unacceptable error signal indicates a need to adjust the coefficient cyclic equalizer vector to yield an acceptable comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector.
摘要:
A system in one embodiment includes a global PLL circuit comprising multiple inputs, each input being for receiving an error signal associated with an individual channel; and a delay compensation circuit coupled to the global PLL circuit. A method in one embodiment includes receiving multiple error signals, each error signal being associated with an individual channel; applying one or more delay compensation signals to the error signals; and outputting phase error output signals for each of the channels.
摘要:
A 16-State adaptive NPML detector is provided for a tape drive which addresses weaknesses of a conventional fixed, 8-state EPR4 detector. Rather than having a fixed target channel, the detector is programmable to allow a range of target channels and can support “classical” partial response channels such as PR4 or EPR4 by programming predictor or whitening filter coefficients. In one embodiment, two filter coefficients may be set via XREG inputs or dynamically determined through the use of an LMS algorithm allowing the detector to adapt the predictor coefficients as data is being read. Another embodiment provides a detector for an EPR4 target in which the whitening filter has one coefficient. Components of the detection system include the detector itself, an LMS engine, a coefficient engine and a noise predictive or whitening filter. Coefficients from the LMS engine may be loaded or stored dynamically based upon conditions in the tape drive.
摘要:
In one embodiment, a method includes applying one or more whitening filters to an input stream of digitized samples from a magnetic data channel to produce a filtered sequence, performing one or more branch metric calculations to the filtered sequence to produce a branch metric, and applying a multi-state data-dependent noise-predictive maximum likelihood (DD-NPML) detector to the branch metric to produce an output stream. In another embodiment, a multi-channel data storage system includes a head for reading data from a storage medium, logic for applying one or more whitening filters to an input stream of digitized samples from a magnetic data channel to produce a filtered sequence, logic for performing one or more branch metric calculations to the filtered sequence to produce a branch metric, and logic for applying a multi-state DD-NPML detector to the branch metric to produce an output stream. Other systems and methods are described as well.
摘要:
Methods, apparatus and computer programs are provided for multiplication-free identification of the impulse response of an oversampled data channel. An input comprising a pseudo-random binary sequence of L symbols is supplied to the channel at a symbol rate of 1/T. A channel output is produced by sampling a channel output signal corresponding to the input with a sampling interval TS=(q/p)T, where q and p are relative prime integers with q
摘要:
A system in one embodiment includes multiple analog inputs for receiving readback signals, an analog to digital converter coupled to each of the analog inputs for converting the readback signals to digital signals, a buffer coupled to outputs of the analog to digital converters for at least temporarily storing the digital signals, and a digital processing section also coupled to outputs of the analog to digital converters for processing the digital signals for reconstructing data therefrom. A method in one embodiment includes receiving multiple channels of analog readback signals from a magnetic head, converting the analog signals in each channel to digital signals, buffering the digital signals, and outputting the buffered digital signals. A method in another embodiment includes receiving a readback waveform from a magnetic storage device, reducing a frequency offset of the readback waveform, and generating a synchronized, oversampled waveform from the readback waveform.
摘要:
A system in one embodiment includes a global PLL circuit comprising multiple inputs, each input being for receiving an error signal associated with an individual channel; and a delay compensation circuit coupled to the global PLL circuit. A method in one embodiment includes receiving multiple error signals, each error signal being associated with an individual channel; applying one or more delay compensation signals to the error signals; and outputting phase error output signals for each of the channels.
摘要:
Provided is a read channel incorporated in a storage device to process signals read from a storage medium. The read channel includes an equalizer equalizing input read signals to produce equalizer output signals. A detector senses an adjusted equalizer output signal to determine an output value comprising data represented by the input read signals. An equalizer adaptor receives the output value from the detector to determine a first error signal used to adjust the equalizer operations. A component adjusts the equalizer output signals being transmitted to the detector, wherein the component is adjusted by a second error signal calculated from the output value from the detector, wherein the first and second error signals are different.