公开(公告)号：US20110084960A1

公开(公告)日：2011-04-14

申请号：US12897375

申请日：2010-10-04

申请人： Hiroyuki Miyake ,  Seiko Amano

发明人： Hiroyuki Miyake ,  Seiko Amano

IPC分类号： G09G5/00 ,  G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/0267 ,  G09G2320/0223 ,  G09G2320/0285

摘要： The shift register includes first to fourth flip-flops. A first clock signal which is in a first voltage state in a first period and in a second voltage state in second to fourth periods is input to the first flip-flop. A second clock signal which is in the first voltage state in the second period and in the second voltage state in the third period and the fourth period is input to the second flip-flop. A third clock signal which is in the second voltage state in the first, second, and fourth periods and in the first voltage state in the third period is input to the third flip-flop. A fourth clock signal which is in the second voltage state in the first and second periods and in the first voltage state in the fourth period is input to the fourth flip-flop.

摘要翻译： 移位寄存器包括第一至第四触发器。 在第一时间段中处于第一电压状态并且在第二至第四周期中处于第二电压状态的第一时钟信号被输入到第一触发器。 第二时钟信号在第二周期和第四周期中的第二周期和第二电压状态下处于第一电压状态，并被输入到第二触发器。 第三时钟信号在第一，第二和第四周期处于第二电压状态，并且在第三周期中处于第一电压状态，被输入到第三触发器。 第四时钟信号在第一和第二周期处于第二电压状态，并且在第四周期中处于第一电压状态，被输入到第四触发器。

公开(公告)号：US09208710B2

公开(公告)日：2015-12-08

申请号：US13017065

申请日：2011-01-31

申请人： Ryota Fukumoto ,  Mitsuaki Osame ,  Hiroyuki Miyake ,  Yoshifumi Tanada ,  Seiko Amano

发明人： Ryota Fukumoto ,  Mitsuaki Osame ,  Hiroyuki Miyake ,  Yoshifumi Tanada ,  Seiko Amano

IPC分类号： G09G3/20 ,  G02F1/1345 ,  G09G3/32 ,  H01L27/12

CPC分类号： G09G3/20 ,  G02F1/1345 ,  G09G3/3225 ,  G09G2300/0426 ,  G09G2310/0275 ,  G09G2330/02 ,  H01L27/12

摘要： The present invention provides a semiconductor device in which a power line is not affected by noise due to a voltage drop caused by instantaneous high-current consumption in the buffer portion and that has no possibility that a logic portion malfunctions. In a case where the same potential is supplied to a logic portion and a buffer portion, by a method in which separate FPC terminals are used for the logic portion and the buffer portion, or by a method in which the FPC terminal is shared but a power line is branched for the logic portion and the buffer portion at a point close to the FPC terminal, a problem that the logic portion is affected by noise generated by a voltage drop of the power line due to instantaneous high-current consumption in the buffer portion can be prevented.

摘要翻译： 本发明提供一种半导体器件，其中电源线由于由缓冲器部分中的瞬时大电流消耗引起的电压降而不受噪声影响，并且不可能使逻辑部分发生故障。 在将逻辑部分和缓冲部分使用单独的FPC终端的方法或通过共享FPC终端的方法而将逻辑部分和缓冲部分提供相同的电位的情况下， 电源线在逻辑部分和缓冲部分分配在靠近FPC终端的点处，由于缓冲器中的瞬时大电流消耗，逻辑部分受到电力线的电压降产生的噪声的影响 可以防止部分。

公开(公告)号：US08710734B2

公开(公告)日：2014-04-29

申请号：US13612249

申请日：2012-09-12

申请人： Seiko Amano

发明人： Seiko Amano

IPC分类号： H01L33/08

CPC分类号： H01L27/3276 ,  H01L27/1214 ,  H01L27/1244 ,  H01L27/3262 ,  H01L51/5246 ,  H01L51/5253 ,  H01L2251/5338 ,  H05B33/04

摘要： It is an object of the present invention to prevent an insulating film from peeling in a section where the insulating film is adjacent to a sealing region. Over a first substrate 104, a pixel portion 100 provided with a light emitting element, a source driver 101, a gate driver 102, and a sealing region 103 are provided. A light emitting element is sealed between the first substrate 104 and a second substrate 110 by a sealant 108. An insulating film 107 serves as a partition wall of the light emitting element. An end portion of the insulating film 107 which is adjacent to the sealing region 103 does not overlap with a step formed by a side surface and an upper surface of a conductive film 106 which serves as a wiring.

摘要翻译： 本发明的目的是防止绝缘膜在绝缘膜与密封区域相邻的部分中剥离。 在第一基板104上设置有设置有发光元件的像素部分100，源极驱动器101，栅极驱动器102和密封区域103。 发光元件通过密封剂108密封在第一基板104和第二基板110之间。绝缘膜107用作发光元件的分隔壁。 与密封区域103相邻的绝缘膜107的端部与由用作布线的导电膜106的侧面和上表面形成的台阶不重叠。

公开(公告)号：US08442183B2

公开(公告)日：2013-05-14

申请号：US13036140

申请日：2011-02-28

申请人： Seiko Amano ,  Kouhei Toyotaka ,  Hiroyuki Miyake ,  Aya Miyazaki ,  Hideaki Shishido ,  Koji Kusunoki

发明人： Seiko Amano ,  Kouhei Toyotaka ,  Hiroyuki Miyake ,  Aya Miyazaki ,  Hideaki Shishido ,  Koji Kusunoki

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G3/3696 ,  G09G2300/0809 ,  G09G2310/0286 ,  G11C19/184 ,  H01L25/03 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/127 ,  H01L27/1288 ,  H01L2924/0002 ,  H03K19/0013 ,  H05K7/02 ,  H01L2924/00

摘要： An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.

摘要翻译： 目的在于提供能够稳定运行的脉冲信号输出电路和包括脉冲信号输出电路的移位寄存器。 根据所公开的发明的一个实施例的脉冲信号输出电路包括第一至第十晶体管。 沟道宽度W与第一晶体管的沟道长度L和第三晶体管的W / L的比W / L分别大于第六晶体管的W / L。 第五晶体管的W / L大于第六晶体管的W / L。 第五晶体管的W / L等于第七晶体管的W / L。 第三晶体管的W / L大于第四晶体管的W / L。 通过这样的结构，可以提供能够稳定运行的脉冲信号输出电路和包括脉冲信号输出电路的移位寄存器。

公开(公告)号：US08334495B2

公开(公告)日：2012-12-18

申请号：US12487287

申请日：2009-06-18

申请人： Jun Koyama ,  Seiko Amano

发明人： Jun Koyama ,  Seiko Amano

IPC分类号： G01J1/44

CPC分类号： G01J1/44 ,  G01J2001/4426 ,  H03F3/08

摘要： A photometric device with a wide dynamic range. The photometric device includes a constant current generation circuit, a fixed clock signal generation circuit which generates a fixed clock signal having a fixed frequency, a photoelectric conversion element, a variable clock signal generation circuit, and a digital signal generation circuit. The fixed clock signal generation circuit generates a fixed clock signal that oscillates at a fixed frequency, from constant current. The variable clock signal generation circuit generates a variable clock signal that oscillates at a frequency proportional to the amount of photocurrent, from photocurrent generated in the photoelectric conversion element. The digital signal generation circuit sets a measurement period using the fixed clock signal, counts the number of pulses of the variable clock signal that oscillates for the measurement period, and outputs a digital signal including the count value as data.

摘要翻译： 具有宽动态范围的光度测量装置。 测光装置包括恒流产生电路，产生具有固定频率的固定时钟信号的固定时钟信号产生电路，光电转换元件，可变时钟信号产生电路和数字信号产生电路。 固定时钟信号产生电路产生固定时钟信号，其以恒定电流以固定频率振荡。 可变时钟信号发生电路产生与光电转换元件中产生的光电流成比例的与光电流量成比例的频率的可变时钟信号。 数字信号发生电路使用固定时钟信号设置测量周期，对在测量周期中振荡的可变时钟信号的脉冲数进行计数，并将包括计数值的数字信号作为数据输出。

公开(公告)号：US09117537B2

公开(公告)日：2015-08-25

申请号：US13111064

申请日：2011-05-19

申请人： Seiko Amano ,  Hiroyuki Miyake

发明人： Seiko Amano ,  Hiroyuki Miyake

IPC分类号： G06F3/038 ,  G11C19/28 ,  G09G5/00 ,  G09G3/32 ,  G09G3/36

CPC分类号： G09G3/3677 ,  G06F1/3265 ,  G06F3/038 ,  G09G3/3266 ,  G09G5/008 ,  G09G2300/0809 ,  G09G2300/0871 ,  G09G2310/0205 ,  G09G2310/0248 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0247 ,  G09G2330/021 ,  G11C19/28 ,  H01L27/124

摘要： In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a bath mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.

摘要翻译： 在移位寄存器的脉冲输出电路中，连接到与下一级的脉冲输出电路连接的输出部中的晶体管的电源线被设定为低电位驱动电压，电源线 连接到连接到扫描信号线的输出部分中的晶体管被​​设置为可变电位驱动电压。 可变电位驱动电压是正常模式下的低电位驱动电压，可以是高电位驱动电压，也可以是槽模式中的低电位驱动电压。 在批量模式中，可以在批次中以相同的定时将显示扫描信号输出到多条扫描信号线。

公开(公告)号：US08153954B2

公开(公告)日：2012-04-10

申请号：US12512280

申请日：2009-07-30

申请人： Seiko Amano ,  Hiroyuki Miyake

发明人： Seiko Amano ,  Hiroyuki Miyake

IPC分类号： H01J40/14

CPC分类号： H03K4/06

摘要： To output a digital signal corresponding to illuminance without being adversely affected by circuit delay. A photoelectric conversion device includes a photoelectric conversion element; a ramp-wave output circuit; a first comparator for comparing the ramp-wave signal and a first potential; a second comparator for comparing the ramp-wave signal and a second potential; a flip-flop circuit for generating a clock signal whose frequency is changed in accordance with the amount of photocurrent; a circuit for calculating a negative OR of the output signal of the first comparator and the output signal of the second comparator; a counter circuit for counting the pulse number of the clock signal; and a pulse output circuit for generating a period during which the pulse number is counted in the counter circuit. The pulse output circuit includes a switch for stopping the generation of the period during which the pulse number is counted.

摘要翻译： 输出对应于照度的数字信号，而不受电路延迟的不利影响。 光电转换装置包括光电转换元件; 斜坡输出电路; 第一比较器，用于比较斜坡波信号和第一电位; 第二比较器，用于比较斜坡波信号和第二电位; 用于产生频率根据光电流量而变化的时钟信号的触发器电路; 用于计算第一比较器的输出信号和第二比较器的输出信号的负OR的电路; 用于对时钟信号的脉冲数进行计数的计数器电路; 以及用于产生在计数器电路中对脉冲数进行计数的周期的脉冲输出电路。 脉冲输出电路包括用于停止脉冲数被计数的周期的产生的开关。

公开(公告)号：US20110285675A1

公开(公告)日：2011-11-24

申请号：US13111064

申请日：2011-05-19

申请人： Seiko Amano ,  Hiroyuki Miyake

发明人： Seiko Amano ,  Hiroyuki Miyake

IPC分类号： G06F3/038 ,  G11C19/00 ,  H03K3/00

CPC分类号： G09G3/3677 ,  G06F1/3265 ,  G06F3/038 ,  G09G3/3266 ,  G09G5/008 ,  G09G2300/0809 ,  G09G2300/0871 ,  G09G2310/0205 ,  G09G2310/0248 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0247 ,  G09G2330/021 ,  G11C19/28 ,  H01L27/124

摘要： In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a bath mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.

摘要翻译： 在移位寄存器的脉冲输出电路中，连接到与下一级的脉冲输出电路连接的输出部中的晶体管的电源线被设定为低电位驱动电压，电源线 连接到连接到扫描信号线的输出部分中的晶体管被​​设置为可变电位驱动电压。 可变电位驱动电压是正常模式下的低电位驱动电压，可以是高电位驱动电压，也可以是槽模式中的低电位驱动电压。 在批量模式中，可以在批次中以相同的定时将显示扫描信号输出到多条扫描信号线。

公开(公告)号：US20100327739A1

公开(公告)日：2010-12-30

申请号：US12874372

申请日：2010-09-02

申请人： Seiko Amano

发明人： Seiko Amano

IPC分类号： H05B33/04

CPC分类号： H01L27/3276 ,  H01L27/1214 ,  H01L27/1244 ,  H01L27/3262 ,  H01L51/5246 ,  H01L51/5253 ,  H01L2251/5338 ,  H05B33/04

摘要： It is an object of the present invention to prevent an insulating film from peeling in a section where the insulating film is adjacent to a sealing region. Over a first substrate 104, a pixel portion 100 provided with a light emitting element, a source driver 101, a gate driver 102, and a sealing region 103 are provided. A light emitting element is sealed between the first substrate 104 and a second substrate 110 by a sealant 108. An insulating film 107 serves as a partition wall of the light emitting element. An end portion of the insulating film 107 which is adjacent to the sealing region 103 does not overlap with a step formed by a side surface and an upper surface of a conductive film 106 which serves as a wiring.

摘要翻译： 本发明的目的是防止绝缘膜在绝缘膜与密封区域相邻的部分中剥离。 在第一基板104上设置有设置有发光元件的像素部分100，源极驱动器101，栅极驱动器102和密封区域103。 发光元件通过密封剂108密封在第一基板104和第二基板110之间。绝缘膜107用作发光元件的分隔壁。 与密封区域103相邻的绝缘膜107的端部与由用作布线的导电膜106的侧面和上表面形成的台阶不重叠。

公开(公告)号：US20070164675A1

公开(公告)日：2007-07-19

申请号：US11652487

申请日：2007-01-12

申请人： Seiko Amano

发明人： Seiko Amano

IPC分类号： H01J1/62 ,  H01J63/04

CPC分类号： H01L27/3276 ,  H01L27/1214 ,  H01L27/1244 ,  H01L27/3262 ,  H01L51/5246 ,  H01L51/5253 ,  H01L2251/5338 ,  H05B33/04

摘要： It is an object of the present invention to prevent an insulating film from peeling in a section where the insulating film is adjacent to a sealing region. Over a first substrate 104, a pixel portion 100 provided with a light emitting element, a source driver 101, a gate driver 102, and a sealing region 103 are provided. A light emitting element is sealed between the first substrate 104 and a second substrate 110 by a sealant 108. An insulating film 107 serves as a partition wall of the light emitting element. An end portion of the insulating film 107 which is adjacent to the sealing region 103 does not overlap with a step formed by a side surface and an upper surface of a conductive film 106 which serves as a wiring.

摘要翻译： 本发明的目的是防止绝缘膜在绝缘膜与密封区域相邻的部分中剥离。 在第一基板104上设置有设置有发光元件的像素部分100，源极驱动器101，栅极驱动器102和密封区域103。 发光元件通过密封剂108密封在第一基板104和第二基板110之间。 绝缘膜107用作发光元件的分隔壁。 与密封区域103相邻的绝缘膜107的端部与由用作布线的导电膜106的侧面和上表面形成的台阶不重叠。