公开(公告)号：US20110224369A1

公开(公告)日：2011-09-15

申请号：US13041831

申请日：2011-03-07

申请人： Seong Do KIM ,  Tae Byoung OH ,  Tae Houng JEONG

发明人： Seong Do KIM ,  Tae Byoung OH ,  Tae Houng JEONG

IPC分类号： C08L67/02 ,  B29C47/00 ,  C08G63/672 ,  C08G63/183

CPC分类号： C08J5/18 ,  B29C47/0021 ,  B29C47/0057 ,  B29C55/04 ,  B29C61/003 ,  B29C63/38 ,  B29K2067/00 ,  B29K2105/02 ,  C08G63/183 ,  C08J2367/02 ,  C09D5/26 ,  Y10T428/1328 ,  Y10T428/1331 ,  Y10T428/31786

摘要： A heat-shrinkable polyester film having a heat-shrinkage change per degree Celsius (%/° C.) along the main shrinkage direction of 1.5 to 3.0 in the range of 60° C. to 70° C., 2.5 to 3.5 in the range of 70° C. to 80° C., 1.0 to 2.0 in the range of 80° C. to 90° C., and 0.1 to 1.0 in the range of 90° C. to 100° C., has a good appearance quality after shrinkage and thus suitable for a wrapping material, particularly a label for a bottle.

摘要翻译： 沿着主收缩方向的热收缩率变化为每摄氏度（％/℃）为1.5〜3.0的热收缩性聚酯膜为60〜70℃，2.5〜3.5 在80℃至80℃的范围内，在80℃至90℃的范围内为1.0至2.0，在90℃至100℃的范围内为0.1至1.0，具有良好的 收缩后的外观质量因此适合于包装材料，特别是瓶子的标签。

公开(公告)号：US20110204944A1

公开(公告)日：2011-08-25

申请号：US13098332

申请日：2011-04-29

申请人： Ja Yol LEE ,  Seong Do KIM ,  Mun Yang PARK ,  Cheon Soo KIM ,  Hyun Kyu YU

发明人： Ja Yol LEE ,  Seong Do KIM ,  Mun Yang PARK ,  Cheon Soo KIM ,  Hyun Kyu YU

IPC分类号： H03L7/08

CPC分类号： H03L7/16 ,  H03L7/095 ,  H03L7/099 ,  H03L7/103 ,  H03L2207/50

摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.

摘要翻译： 提供了数字锁定检测器和使用该锁定检测器的频率合成器。 数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

公开(公告)号：US20100144281A1

公开(公告)日：2010-06-10

申请号：US12628684

申请日：2009-12-01

申请人： Seong Do KIM ,  Ja Yol LEE ,  Jae Hoon SHIM ,  Hyun Kyu YU

发明人： Seong Do KIM ,  Ja Yol LEE ,  Jae Hoon SHIM ,  Hyun Kyu YU

IPC分类号： H04B15/00

CPC分类号： H04B1/123

摘要： An apparatus and method for removing an interference signal using a selective frequency phase converter are disclosed. The apparatus for removing an interference signal using a selective frequency phase converter includes: a first phase converter configured to convert a phase of a received RF signal to differentially output first and second signals having a phase difference of 180° from each other; a second phase converter configured to receive the first signal and selectively convert the phase of a particular frequency band; a third phase converter configured to receive the second signal and selectively convert the phase of a particular frequency band; a timing controller configured to correct a signal delay time between the output from the second phase converter and that of the third phase converter; and an adder configured to add an output from the second phase converter and an output from the third phase converter, wherein the second and third phase converters phase-convert the first and second signals such that the phases of the signals of the particular frequency bands do not have a phase difference of 180° from each other.

摘要翻译： 公开了一种使用选择性频率相位变换器去除干扰信号的装置和方法。 使用选择性频率相位变换器去除干扰信号的装置包括：第一相位转换器，被配置为将接收的RF信号的相位转换为差分地输出具有彼此相差180°的第一和第二信号; 第二相转换器，被配置为接收第一信号并选择性地转换特定频带的相位; 配置为接收所述第二信号并选择性地转换特定频带的相位的第三相位转换器; 定时控制器，被配置为校正来自第二相位转换器的输出和第三相位转换器的输出之间的信号延迟时间; 以及加法器，被配置为将来自第二相位转换器的输出和来自第三相位转换器的输出相加，其中第二和第三相位转换器对第一和第二信号进行相位转换，使得特定频带的信号的相位做 彼此之间没有180°的相位差。

公开(公告)号：US20070241844A1

公开(公告)日：2007-10-18

申请号：US11690219

申请日：2007-03-23

申请人： Cheon Soo KIM ,  Myung Shin KWAK ,  Seong Do KIM ,  Mun Yang PARK ,  Hyun Kyu YU ,  Hee Bum JUNG

发明人： Cheon Soo KIM ,  Myung Shin KWAK ,  Seong Do KIM ,  Mun Yang PARK ,  Hyun Kyu YU ,  Hee Bum JUNG

IPC分类号： H01P3/08

CPC分类号： H01P3/003

摘要： A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.

摘要翻译： 提供了一种使用多层互连CMOS技术的共面波导CPW。 在包括设置在基板上的层间绝缘体的CPW中，设置在层间绝缘体上的金属多层和最下层的接地线的接地线 - 信号线 - 由最上层金属层形成的接地线连接到 最上层的地线，中间金属层被设计成逐渐增加或减小宽度或不均匀，以便使超高频率扩展的面积最大化，由此最小化CPW损耗并最大化慢波效应。 结果，可以提高超高频电路的性能并使电路小型化。