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    Method for forming a wiring of a semiconductor device, method for forming a metal layer of a semiconductor device and apparatus for performing the same
    5.
    发明授权
    Method for forming a wiring of a semiconductor device, method for forming a metal layer of a semiconductor device and apparatus for performing the same 有权
    用于形成半导体器件的布线的方法，用于形成半导体器件的金属层的方法及其执行方法

    公开(公告)号：US07105444B2

    公开(公告)日：2006-09-12

    申请号：US10857253

    申请日：2004-05-28

    申请人： Kyung-In Choi ,  Sang-Bom Kang ,  Seong-Geon Park ,  You-Kyoung Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Woo Lee

    发明人： Kyung-In Choi ,  Sang-Bom Kang ,  Seong-Geon Park ,  You-Kyoung Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Woo Lee

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28556 ,  C23C16/34 ,  C23C16/45553 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/76862 ,  H01L21/76867 ,  H01L21/76877

    摘要： In a method for forming a wiring of a semiconductor device using an atomic layer deposition, an insulating interlayer is formed on a substrate. Tantalum amine derivatives represented by a chemical formula Ta(NR1)(NR2R3)3 in which R1, R2 and R3 represent H or C1–C6 alkyl group are introduced onto the insulating interlayer. A portion of the tantalum amine derivatives is chemisorbed on the insulating interlayer. The rest of tantalum amine derivatives non-chemisorbed on the insulating interlayer is removed from the insulating interlayer. A reacting gas is introduced onto the insulating interlayer. A ligand in the tantalum amine derivatives chemisorbed on the insulating interlayer is removed from the tantalum amine derivatives by a chemical reaction between the reacting gas and the ligand to form a solid material including tantalum nitride. The solid material is accumulated on the insulating interlayer through repeating the above processes to form a wiring.

    摘要翻译： 在使用原子层沉积形成半导体器件的布线的方法中，在基板上形成绝缘中间层。 由化学式Ta（NR 1）3（NR 2 R 3）3表示的钽胺衍生物，其中 R 1，R 2和R 3代表H或C 1 -C 6 >烷基引入到绝缘中间层上。 一部分钽胺衍生物被化学吸附在绝缘中间层上。 在绝缘中间层上除去非化学吸附在绝缘中间层上的其余的钽胺衍生物。 将反应气体引入到绝缘中间层上。 化学吸附在绝缘中间层上的钽胺衍生物中的配体通过反应气体和配位体之间的化学反应从钽胺衍生物中除去以形成包括氮化钽的固体材料。 通过重复上述处理，将固体材料积聚在绝缘层间，形成布线。

    Semiconductor devices having metal containing N-type and P-type gate electrodes and methods of forming the same
    8.
    发明授权
    Semiconductor devices having metal containing N-type and P-type gate electrodes and methods of forming the same 有权
    具有含有N型和P型栅电极的金属的半导体器件及其形成方法

    公开(公告)号：US07056776B2

    公开(公告)日：2006-06-06

    申请号：US10940159

    申请日：2004-09-14

    申请人： Seong-Geon Park ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  You-Kyoung Lee

    发明人： Seong-Geon Park ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  You-Kyoung Lee

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L21/823842 ,  H01L27/0922

    摘要： A semiconductor device has at least two different gate electrodes. The two different gate electrodes include a first gate electrode on a first gate insulation layer. The first gate electrode includes a first metal-containing conductive pattern on the first gate insulation layer and a second metal-containing conductive pattern. A second gate electrode is provided on a second gate insulation layer and includes a third metal-containing conductive material on the second gate insulation layer. The first metal-containing conductive pattern and the third metal-containing conductive pattern have different work functions from each other. A surface of the second metal-containing conductive pattern and a surface of the third metal-containing conductive pattern are substantially planar. Methods of fabrication such semiconductor devices are also provided.

    摘要翻译： 半导体器件具有至少两个不同的栅电极。 两个不同的栅电极包括在第一栅绝缘层上的第一栅电极。 第一栅电极包括第一栅绝缘层上的第一含金属导电图案和第二含金属导电图案。 第二栅电极设置在第二栅绝缘层上，并且在第二栅绝缘层上包括第三含金属导电材料。 第一含金属导电图案和第三含金属导电图案具有彼此不同的功函数。 第二含金属导电图案的表面和第三含金属导电图案的表面基本上是平面的。 还提供了制造这种半导体器件的方法。

    Method for forming a wiring of a semiconductor device, method for forming a metal layer of a semiconductor device and apparatus for performing the same
    9.
    发明授权
    Method for forming a wiring of a semiconductor device, method for forming a metal layer of a semiconductor device and apparatus for performing the same 有权
    用于形成半导体器件的布线的方法，用于形成半导体器件的金属层的方法及其执行方法

    公开(公告)号：US07452811B2

    公开(公告)日：2008-11-18

    申请号：US11425970

    申请日：2006-06-22

    申请人： Kyung-In Choi ,  Sang-Bom Kang ,  Seong-Geon Park ,  You-Kyoung Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Woo Lee

    发明人： Kyung-In Choi ,  Sang-Bom Kang ,  Seong-Geon Park ,  You-Kyoung Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Woo Lee

    IPC分类号： H01L21/443

    CPC分类号： H01L21/28556 ,  C23C16/34 ,  C23C16/45553 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/76862 ,  H01L21/76867 ,  H01L21/76877

    摘要： In a method for forming a wiring of a semiconductor device using an atomic layer deposition, an insulating interlayer is formed on a substrate. Tantalum amine derivatives represented by a chemical formula Ta(NR1)(NR2R3)3 in which R1, R2 and R3 represent H or C1-C6 alkyl group are introduced onto the insulating interlayer. A portion of the tantalum amine derivatives is chemisorbed on the insulating interlayer. The rest of tantalum amine derivatives non-chemisorbed on the insulating interlayer is removed from the insulating interlayer. A reacting gas is introduced onto the insulating interlayer. A ligand in the tantalum amine derivatives chemisorbed on the insulating interlayer is removed from the tantalum amine derivatives by a chemical reaction between the reacting gas and the ligand to form a solid material including tantalum nitride. The solid material is accumulated on the insulating interlayer through repeating the above processes to form a wiring.

    摘要翻译： 在使用原子层沉积形成半导体器件的布线的方法中，在基板上形成绝缘中间层。 由化学式Ta（NR 1）3（NR 2 R 3）3表示的钽胺衍生物，其中 R 1，R 2和R 3代表H或C 1 -C 6 >烷基引入到绝缘中间层上。 一部分钽胺衍生物被化学吸附在绝缘中间层上。 在绝缘中间层上除去非化学吸附在绝缘中间层上的其余的钽胺衍生物。 将反应气体引入到绝缘中间层上。 化学吸附在绝缘中间层上的钽胺衍生物中的配体通过反应气体和配位体之间的化学反应从钽胺衍生物中除去以形成包括氮化钽的固体材料。 通过重复上述处理，将固体材料积聚在绝缘层间，形成布线。

    Semiconductor devices having metal containing N-type and P-type gate electrodes and methods of forming the same
    10.
    发明申请
    Semiconductor devices having metal containing N-type and P-type gate electrodes and methods of forming the same 有权
    具有含有N型和P型栅电极的金属的半导体器件及其形成方法

    公开(公告)号：US20050064653A1

    公开(公告)日：2005-03-24

    申请号：US10940159

    申请日：2004-09-14

    申请人： Seong-Geon Park ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  You-Kyoung Lee

    发明人： Seong-Geon Park ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  You-Kyoung Lee

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/823842 ,  H01L27/0922

    摘要： A semiconductor device has at least two different gate electrodes. The two different gate electrodes include a first gate electrode on a first gate insulation layer. The first gate electrode includes a first metal-containing conductive pattern on the first gate insulation layer and a second metal-containing conductive pattern. A second gate electrode is provided on a second gate insulation layer and includes a third metal-containing conductive material on the second gate insulation layer. The first metal-containing conductive pattern and the third metal-containing conductive pattern have different work functions from each other. A surface of the second metal-containing conductive pattern and a surface of the third metal-containing conductive pattern are substantially planar. Methods of fabrication such semiconductor devices are also provided.

    摘要翻译： 半导体器件具有至少两个不同的栅电极。 两个不同的栅电极包括在第一栅绝缘层上的第一栅电极。 第一栅电极包括第一栅绝缘层上的第一含金属导电图案和第二含金属导电图案。 第二栅电极设置在第二栅绝缘层上，并且在第二栅绝缘层上包括第三含金属导电材料。 第一含金属导电图案和第三含金属导电图案具有彼此不同的功函数。 第二含金属导电图案的表面和第三含金属导电图案的表面基本上是平面的。 还提供了制造这种半导体器件的方法。