公开(公告)号：US07245553B2

公开(公告)日：2007-07-17

申请号：US11352142

申请日：2006-02-10

Applicant: Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

Inventor： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC: G11C8/00

CPC classification number: G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

公开(公告)号：US20060143491A1

公开(公告)日：2006-06-29

申请号：US11352131

申请日：2006-02-10

Applicant: Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

Inventor： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC: G06F1/12 ,  G06F1/06 ,  G06F1/04 ,  G11C7/10 ,  G11C8/00 ,  G06F13/42

CPC classification number: G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

公开(公告)号：US20050242888A1

公开(公告)日：2005-11-03

申请号：US10834775

申请日：2004-04-28

Applicant: Seong-hoon Lee ,  Feng Lin

Inventor： Seong-hoon Lee ,  Feng Lin

IPC: H03L7/00 ,  H03L7/083 ,  H03L7/089 ,  H03L7/099 ,  H03L7/10

CPC classification number: H03L7/10 ,  H03L7/083 ,  H03L7/0891 ,  H03L7/0995

Abstract: PLL circuits are provided in which a voltage-controlled oscillator (VCO) comprising one or more voltage-controlled delay units (VCDs) is initialized with the control voltage of a voltage-controlled delay line (VCDL) having substantially identical VCDs. In general, VCDLs provide for faster signal locking than do VCOs. The VCO locks to a frequency of a reference signal at substantially the same time that the VCDL locks to the reference signal. Lock time of the PLL circuit is thereby reduced. A timing circuit prevents the VCO control voltage from being adjusted during phase locking of the VCO. This allows the VCO frequency lock to be maintained during the VCO phase locking. Lock time is thereby further reduced. The timing circuit locks the VCO to a phase of the reference signal by restarting oscillation of the VCO at an appropriate time.

Abstract translation: 提供PLL电路，其中包括一个或多个电压控制延迟单元（VCD）的压控振荡器（VCO）用具有基本相同的VCD的电压控制延迟线（VCDL）的控制电压来初始化。 通常，VCDLs比VCO提供更快的信号锁定。 在与VCDL锁定到参考信号的基本相同的时刻，VCO锁定到参考信号的频率。 因此PLL电路的锁定时间减少。 定时电路防止在VCO的锁相期间调节VCO控制电压。 这允许在VCO锁相期间保持VCO频率锁定。 从而进一步减少锁定时间。 定时电路通过在适当的时间重新启动VCO的振荡将VCO锁定到参考信号的相位。

公开(公告)号：US07528638B2

公开(公告)日：2009-05-05

申请号：US10744206

申请日：2003-12-22

Applicant: Seong-hoon Lee ,  Feng Lin

Inventor： Seong-hoon Lee ,  Feng Lin

IPC: H03L7/06

CPC classification number: H03L7/07 ,  G06F1/10 ,  H03L7/0812 ,  H03L7/0995

Abstract: Clock signal distribution systems with reduced parasitic loading effects are provided. A reference clock is frequency-divided to produce a lower frequency clock signal. A delay-locked loop (DLL) circuit locks to the lower frequency clock signal, and outputs a corresponding lower frequency clock signal for distribution over a long trace. Power consumption caused by parasitic capacitance of the trace is thereby reduced. Parasitic effects associated with clock jitter are also reduced. A frequency multiplying phase-locked loop (PLL) circuit locks to the lower frequency clock signal, and outputs at least one clock signal having a higher frequency than the lower frequency signal.

Abstract translation: 提供具有减小的寄生负载效应的时钟信号分配系统。 参考时钟被分频以产生较低频率的时钟信号。 延迟锁定环（DLL）电路锁定到较低频率时钟信号，并输出相应的较低频率时钟信号，以在较长的轨迹上分布。 因此，由于迹线的寄生电容引起的功耗降低。 与时钟抖动相关的寄生效应也降低。 频率倍增锁相环（PLL）电路锁定到较低频率时钟信号，并且输出具有比低频信号更高频率的至少一个时钟信号。

公开(公告)号：US20060044891A1

公开(公告)日：2006-03-02

申请号：US10931472

申请日：2004-08-31

Applicant: Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

Inventor： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC: G11C7/00

CPC classification number: G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

公开(公告)号：US07251194B2

公开(公告)日：2007-07-31

申请号：US11352078

申请日：2006-02-10

Applicant: Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

Inventor： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC: G11C8/18

CPC classification number: G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

Abstract translation: 存储器系统将命令，地址或写入数据信号从存储器控制器耦合到存储器件，并将数据信号从存储器件读取到存储器控制器。 每个存储器控制器和存储器件中的相应选通发生器电路都产生同相选通信号和正交选通信号。 存储在存储器控制器中的相应输出锁存器中的命令，地址或写入数据信号由来自内部选通发生器电路的同相信号计时。 这些命令，地址或写入数据信号通过从存储器控制器耦合到存储器件的正交选通信号而被锁存在存储器件中的输入锁存器中。 以基本相同的方式，使用由内部选通发生器电路产生的同相和正交选通信号，将读取的数据信号从存储器件耦合到存储器控制器。

公开(公告)号：US07230495B2

公开(公告)日：2007-06-12

申请号：US10834775

申请日：2004-04-28

Applicant: Seong-hoon Lee ,  Feng Lin

Inventor： Seong-hoon Lee ,  Feng Lin

IPC: H03L7/00

CPC classification number: H03L7/10 ,  H03L7/083 ,  H03L7/0891 ,  H03L7/0995

Abstract: PLL circuits are provided in which a voltage-controlled oscillator (VCO) comprising one or more voltage-controlled delay units (VCDs) is initialized with the control voltage of a voltage-controlled delay line (VCDL) having substantially identical VCDs. In general, VCDLs provide for faster signal locking than do VCOs. The VCO locks to a frequency of a reference signal at substantially the same time that the VCDL locks to the reference signal. Lock time of the PLL circuit is thereby reduced. A timing circuit prevents the VCO control voltage from being adjusted during phase locking of the VCO. This allows the VCO frequency lock to be maintained during the VCO phase locking. Lock time is thereby further reduced. The timing circuit locks the VCO to a phase of the reference signal by restarting oscillation of the VCO at an appropriate time.

Abstract translation: 提供PLL电路，其中包括一个或多个电压控制延迟单元（VCD）的压控振荡器（VCO）用具有基本相同的VCD的电压控制延迟线（VCDL）的控制电压来初始化。 通常，VCDLs比VCO提供更快的信号锁定。 在与VCDL锁定到参考信号的基本相同的时刻，VCO锁定到参考信号的频率。 因此PLL电路的锁定时间减少。 定时电路防止在VCO的锁相期间调节VCO控制电压。 这允许在VCO锁相期间保持VCO频率锁定。 从而进一步减少锁定时间。 定时电路通过在适当的时间重新启动VCO的振荡将VCO锁定到参考信号的相位。

公开(公告)号：US07126874B2

公开(公告)日：2006-10-24

申请号：US10931472

申请日：2004-08-31

Applicant: Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

Inventor： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC: G11C8/00

CPC classification number: G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

Abstract translation: 存储器系统将命令，地址或写入数据信号从存储器控制器耦合到存储器件，并将数据信号从存储器件读取到存储器控制器。 每个存储器控制器和存储器件中的相应选通发生器电路都产生同相选通信号和正交选通信号。 存储在存储器控制器中的相应输出锁存器中的命令，地址或写入数据信号由来自内部选通发生器电路的同相信号计时。 这些命令，地址或写入数据信号通过从存储器控制器耦合到存储器件的正交选通信号而被锁存在存储器件中的输入锁存器中。 以基本相同的方式，使用由内部选通发生器电路产生的同相和正交选通信号，将读取的数据信号从存储器件耦合到存储器控制器。

公开(公告)号：US20060140023A1

公开(公告)日：2006-06-29

申请号：US11352078

申请日：2006-02-10

Applicant: Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

Inventor： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC: G11C7/00

CPC classification number: G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

公开(公告)号：US20060133165A1

公开(公告)日：2006-06-22

申请号：US11351836

申请日：2006-02-10

Applicant: Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

Inventor： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC: G11C7/00

CPC classification number: G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.