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公开(公告)号：US08621323B2
公开(公告)日：2013-12-31
申请号：US12353185
申请日：2009-01-13
CPC分类号： G06F12/0246 , G06F11/1008 , G11C7/1039 , G11C7/1051 , G11C16/3436
摘要： The present invention presents methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural examples are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.
摘要翻译： 本发明提出了用于具有写入操作的读取操作的流水线的方法和架构。 特别地，提出了用于流水线数据迁移操作的方法，其允许在控制器被重写之前检查和校正控制器中的数据，但是减少或消除通常会产生的额外时间损失。 描述了许多架构示例来促进这些方法，包括：在存储器中引入两个寄存器，每个寄存器可由控制器独立访问; 允许在写入第二个寄存器时写入第一个存储器寄存器; 在存储器中引入两个寄存器，其中寄存器的内容可以交换。
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公开(公告)号：US07778077B2
公开(公告)日：2010-08-17
申请号：US11383397
申请日：2006-05-15
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C16/349 , G11C16/3495
摘要： A system and methods are given for providing information on the amount of life remaining for a memory having a limited lifespan, such as a flash memory card. For example, it can provide a user with the amount of the memory's expected remaining lifetime in real time units (i.e., hours or days) or as a percentage of estimated initial life. An end of life warning can also be provided. In a particular embodiment, the amount of remaining life (either as a percentage or in real time units) can be based on the average number of erases per block, but augmented by the number of spare blocks or other parameters, so that an end of life warning is given if either the expected amount of remaining life falls below a certain level or the number of spare blocks falls below a safe level.
摘要翻译： 给出了提供关于具有有限寿命的存储器（例如闪存卡）的剩余寿命的信息的系统和方法。 例如，它可以向用户提供实时单位（即，小时或天）中的存储器的预期剩余寿命的量，或作为估计的初始寿命的百分比。 也可以提供生命警告的结束。 在特定实施例中，剩余寿命的量（以百分比或实时单位计）可以基于每个块的平均擦除次数，但是增加了备用块的数量或其他参数，使得结束 如果预期的剩余生命量低于一定水平或备用块数量低于安全水平，则会发出生命警告。
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公开(公告)号：US07523013B2
公开(公告)日：2009-04-21
申请号：US11383384
申请日：2006-05-15
IPC分类号： G06F3/01
CPC分类号： G06F11/008 , G11C16/349 , G11C16/3495
摘要： A system and methods are given for providing information on the amount of life remaining for a memory having a limited lifespan, such as a flash memory card. For example, it can provide a user with the amount of the memory's expected remaining lifetime in real time units (i.e., hours or days) or as a percentage of estimated initial life. An end of life warning can also be provided. In a particular embodiment, the amount of remaining life (either as a percentage or in real time units) can be based on the average number of erases per block, but augmented by the number of spare blocks or other parameters, so that an end of life warning is given if either the expected amount of remaining life falls below a certain level or the number of spare blocks falls below a safe level.
摘要翻译： 给出了提供关于具有有限寿命的存储器（例如闪存卡）的剩余寿命的信息的系统和方法。 例如，它可以向用户提供实时单位（即，小时或天）中的存储器的预期剩余寿命的量，或作为估计的初始寿命的百分比。 也可以提供生命警告的结束。 在特定实施例中，剩余寿命的量（以百分比或实时单位计）可以基于每个块的平均擦除次数，但是增加了备用块的数量或其他参数，使得结束 如果预期的剩余生命量低于一定水平或备用块数量低于安全水平，则会发出生命警告。
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公开(公告)号：US20100023681A1
公开(公告)日：2010-01-28
申请号：US12572844
申请日：2009-10-02
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/0626 , G06F3/0658 , G06F3/0679 , G06F12/0893 , G06F2212/7201 , G06F2212/7203 , G11C14/0036 , G11C14/0045
摘要： The present invention presents a hybrid non-volatile system that uses non-volatile memories based on two or more different non-volatile memory technologies in order to exploit the relative advantages of each these technology with respect to the others. In an exemplary embodiment, the memory system includes a controller and a flash memory, where the controller has a non-volatile RAM based on an alternate technology such as FeRAM. The flash memory is used for the storage of user data and the non-volatile RAM in the controller is used for system control data used by the control to manage the storage of host data in the flash memory. The use of an alternate non-volatile memory technology in the controller allows for a non-volatile copy of the most recent control data to be accessed more quickly as it can be updated on a bit by bit basis. In another exemplary embodiment, the alternate non-volatile memory is used as a cache where data can safely be staged prior to its being written to the to the memory or read back to the host.
摘要翻译： 本发明提出了一种混合非易失性系统，其使用基于两个或多个不同的非易失性存储器技术的非易失性存储器，以利用这些技术相对于其他技术的相对优点。 在示例性实施例中，存储器系统包括控制器和闪存，其中控制器具有基于诸如FeRAM的替代技术的非易失性RAM。 闪存用于存储用户数据，并且控制器中的非易失性RAM用于由控制器用于管理闪存中的主机数据的存储的系统控制数据。 在控制器中使用替代的非易失性存储器技术允许更快速地访问最近的控制数据的非易失性拷贝，因为它可以逐点更新。 在另一个示例性实施例中，备用非易失性存储器用作高速缓存，其中数据可以在其被写入存储器或读回主机之前安全地分级。
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公开(公告)号：US20090125785A1
公开(公告)日：2009-05-14
申请号：US12353185
申请日：2009-01-13
CPC分类号： G06F12/0246 , G06F11/1008 , G11C7/1039 , G11C7/1051 , G11C16/3436
摘要： The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improve are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.
摘要翻译： 本发明提出了用于具有写入操作的读取操作的流水线的方法和架构。 特别地，提出了用于流水线数据迁移操作的方法，其允许在控制器被重写之前检查和校正控制器中的数据，但是减少或消除通常会产生的额外时间损失。 描述了许多架构改进以便于这些方法，包括：在存储器上引入两个寄存器，每个寄存器可由控制器独立访问; 允许在写入第二个寄存器时写入第一个存储器寄存器; 在存储器中引入两个寄存器，其中寄存器的内容可以交换。
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公开(公告)号：US07490283B2
公开(公告)日：2009-02-10
申请号：US10846289
申请日：2004-05-13
CPC分类号： G06F12/0246 , G06F11/1008 , G11C7/1039 , G11C7/1051 , G11C16/3436
摘要： The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improvements are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.
摘要翻译： 本发明提出了用于具有写入操作的读取操作的流水线的方法和架构。 特别地，提出了用于流水线数据迁移操作的方法，其允许在控制器被重写之前检查和校正控制器中的数据，但是减少或消除通常会产生的额外时间损失。 描述了许多架构改进以促进这些方法，包括：在存储器上引入两个寄存器，每个寄存器可由控制器独立访问; 允许在写入第二个寄存器时写入第一个存储器寄存器; 在存储器中引入两个寄存器，其中寄存器的内容可以交换。
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公开(公告)号：US07173852B2
公开(公告)日：2007-02-06
申请号：US11253531
申请日：2005-10-18
IPC分类号： G11C11/34
CPC分类号： G06F11/106 , G06F11/1068 , G11C16/3418 , G11C16/3431 , G11C29/76
摘要： In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase. Data is rewritten when severe errors are found during read operations. Portions of data are corrected and copied within the time limit for read operation. Corrected portions are written to dedicated blocks.
摘要翻译： 为了保持存储在闪速存储器中的数据的完整性，其易于被存储器的相邻区域中的操作干扰，干扰事件导致在变得如此损坏之前读取，校正和重新写入数据，使得有效数据不能 被收回。 当存储器系统具有执行其他高优先级操作时，通过推迟执行某些纠正措施来平衡维护数据完整性和系统性能的有时冲突的需求。 在使用非常大的擦除单位的存储器系统中，以与有效地重写远远小于擦除单位的容量的数据量相一致的方式执行校正处理。 在读取操作期间发现严重错误时，数据被重写。 部分数据在读取操作的时限内得到纠正和复制。 校正的部分被写入专用块。
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公开(公告)号：US20150095546A1
公开(公告)日：2015-04-02
申请号：US14044548
申请日：2013-10-02
IPC分类号： G06F3/06
CPC分类号： G06F12/00 , G06F3/0649 , G06F12/0246 , G06F12/0292 , G06F2212/1036 , G06F2212/7201 , G06F2212/7208 , G06F2212/7211
摘要： A method and system are disclosed for remapping logical addresses between memory banks of discrete or embedded multi-bank storage device. The method may include a controller of a storage device tracking a total erase count for a storage device, determining if an erase count imbalance greater than a threshold exists between banks, and then remapping logical address ranges from the highest erase count bank to the lowest erase count bank to even out wear between the banks. The system may include a controller that may maintain a bank routing table, an erase counting mechanism and execute instructions for triggering a remapping process to remap an amount of logical addresses such that an address range is reduced for a hotter bank and increased for a colder bank.
摘要翻译： 公开了用于重新映射离散或嵌入式多存储存储设备的存储体之间的逻辑地址的方法和系统。 该方法可以包括跟踪存储设备的总擦除计数的存储设备的控制器，确定在存储体之间是否存在大于阈值的擦除计数不平衡，然后将逻辑地址范围从最高擦除计数存储区重新映射到最低擦除 计数银行甚至在银行之间穿戴。 系统可以包括可以维护银行路由表，擦除计数机制和执行指令的控制器，用于触发重映射处理以重新映射逻辑地址的数量，使得对于较热的银行减少地址范围并且对于较冷的银行而言增加 。
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9.发明授权Storing data in parallel in a flash storage device using on chip page shifting between planes 有权在闪存存储设备中并行存储数据，使用片上页面在平面之间切换公开(公告)号：US08775722B2
公开(公告)日：2014-07-08
申请号：US13341543
申请日：2011-12-30
IPC分类号： G06F12/00
CPC分类号： G11C7/1012 , G11C11/5621 , G11C16/10
摘要： Methods and systems are disclosed herein for storing data in a memory device. Data for multiple pages is written in parallel using plane interleaving. For example, in a four plane write, a first set of four pages are written in the following sequence: 0, 1, 2, 3. A second set of four pages, after plane interleaving, are written in the following sequent: 7, 4, 5, 6. After writing the data, the pages of written data are read, page swapped if necessary, and then written into another portion of memory (such as MLC).
摘要翻译： 本文公开了用于将数据存储在存储器件中的方法和系统。 使用平面交错并行写入多页数据。 例如，在四平面写入中，按照以下顺序写入第一组四页：0,1,2,3。在平面交织之后的第二组四页被写入随后的后续步骤：7， 写入数据后，读取写入数据的页面，如果需要，页面交换，然后写入存储器的另一部分（如MLC）。
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公开(公告)号：US08208322B2
公开(公告)日：2012-06-26
申请号：US13108477
申请日：2011-05-16
IPC分类号： G11C7/00
CPC分类号： G06F13/1615 , G06F3/0625 , G06F3/0659 , G06F3/0688 , G06F13/4239 , G11C7/1039 , Y02D10/154
摘要： Methods and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time are useful in the control of concurrent access of memory arrays. One method includes implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays and limiting the number of active arrays operating at one time. The controller is configured to wait for the at least one of the arrays to complete before initiating a transfer to and from a further array.
摘要翻译： 在具有非易失性存储器的存储器系统中使用的方法和装置以及用于从一次访问的多个可用阵列限制非易失性存储器阵列的数量的控制器在对存储器阵列的并发访问的控制中是有用的。 一种方法包括实现用于将数据传送到非易失性存储器阵列和从非易失性存储器阵列传送数据的流水线序列，并限制一次操作的有源阵列的数量。 控制器被配置为等待至少一个数组完成，然后开始向另一阵列传送数据。
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