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    Use of guard bands and phased maintenance operations to avoid exceeding maximum latency requirements in non-volatile memory systems
    2.
    发明授权
    Use of guard bands and phased maintenance operations to avoid exceeding maximum latency requirements in non-volatile memory systems 有权
    使用保护频段和分阶段的维护操作，以避免在非易失性存储器系统中超过最大延迟要求

    公开(公告)号：US08417876B2

    公开(公告)日：2013-04-09

    申请号：US12821759

    申请日：2010-06-23

    申请人： Sergey Anatolievich Gorobets ,  Robert George Young ,  Alan David Bennett

    发明人： Sergey Anatolievich Gorobets ,  Robert George Young ,  Alan David Bennett

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0246 ,  G06F2212/7205

    摘要： Techniques are presented for performing maintenance operations, such as garbage collection, on non-volatile memory systems will still respecting the maximum latency, or time-out, requirements of a protocol. A safety guard band in the space available for storing host data, control data, or both, is provided. If, on an access of the memory, it is determined that the guard band space is exceeded, the system uses a recovery back to the base state by triggering and prioritizing clean-up operations to re-establish all safety guard bands without breaking the timing requirements. To respect these timing requirements, the operations are split into portions and done in a phased manner during allowed latency periods.

    摘要翻译： 提出了用于执行维护操作（例如垃圾收集）的技术，在非易失性存储器系统上仍将遵守协议的最大等待时间或超时要求。 提供了可用于存储主机数据，控制数据或两者的空间中的安全保护带。 如果在存储器的访问上确定超过了保护带空间，则系统通过触发并清除清除操作的优先级将恢复恢复到基本状态，以重新建立所有安全保护带而不破坏时序 要求。 为了遵守这些时序要求，在允许的等待时间期间，操作被分成多个部分并以分阶段的方式完成。

    Adaptive Deterministic Grouping of Blocks into Multi-Block Units
    4.
    发明申请
    Adaptive Deterministic Grouping of Blocks into Multi-Block Units 有权
    块自适应确定性分组成多块单位

    公开(公告)号：US20110191530A1

    公开(公告)日：2011-08-04

    申请号：US13084396

    申请日：2011-04-11

    申请人： Carlos J. Gonzalez ,  Alan Douglas Bryce ,  Sergey Anatolievich Gorobets ,  Alan David Bennett

    发明人： Carlos J. Gonzalez ,  Alan Douglas Bryce ,  Sergey Anatolievich Gorobets ,  Alan David Bennett

    IPC分类号： G06F12/00

    CPC分类号： G11C29/76 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C29/808

    摘要： The present invention presents techniques for the linking of physical blocks of a non-volatile memory into composite logical structures or “metablocks”. After determining an initial linking of good physical blocks into metablocks, a record of the linking is maintained in the non-volatile memory where it can be readily accessed when needed. In one set of embodiments, the initially linking is deterministically formed according to an algorithm and can be optimized according to the pattern of any bad blocks in the memory. As additional bad blocks arise, the linking is updated using by replacing the bad blocks in a linking with good blocks, preferably in the same sub-array of the memory as the block that they are replacing.

    摘要翻译： 本发明提出了用于将非易失性存储器的物理块链接到复合逻辑结构或“元区块”中的技术。 在确定好的物理块到元区块的初始链接之后，在非易失性存储器中维护链接的记录，在需要时可以容易地访问。 在一组实施例中，根据算法确定性地形成初始链接，并且可以根据存储器中的任何坏块的模式进行优化。 随着额外的坏块出现，链接被更新，通过替换与优质块链接的坏块，优选地与它们所替换的块相同的存储器子阵列来更新。

    Adaptive Deterministic Grouping of Blocks into Multi-Block Units
    5.
    发明申请
    Adaptive Deterministic Grouping of Blocks into Multi-Block Units 有权
    块自适应确定性分组成多块单位

    公开(公告)号：US20090292944A1

    公开(公告)日：2009-11-26

    申请号：US12512282

    申请日：2009-07-30

    申请人： Carlos J. Gonzalez ,  Alan Douglas Bryce ,  Sergey Anatolievich Gorobets ,  Alan David Bennett

    发明人： Carlos J. Gonzalez ,  Alan Douglas Bryce ,  Sergey Anatolievich Gorobets ,  Alan David Bennett

    IPC分类号： G06F11/20

    CPC分类号： G11C29/76 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C29/808

    摘要： The present invention presents techniques for the linking of physical blocks of a non-volatile memory into composite logical structures or “metablocks”. After determining an initial linking of good physical blocks into metablocks, a record of the linking is maintained in the non-volatile memory where it can be readily accessed when needed. In one set of embodiments, the initially linking is deterministically formed according to an algorithm and can be optimized according to the pattern of any bad blocks in the memory. As additional bad blocks arise, the linking is updated using by replacing the bad blocks in a linking with good blocks, preferably in the same sub-array of the memory as the block that they are replacing.

    摘要翻译： 本发明提出了用于将非易失性存储器的物理块链接到复合逻辑结构或“元区块”中的技术。 在确定好的物理块到元区块的初始链接之后，在非易失性存储器中维护链接的记录，在需要时可以容易地访问。 在一组实施例中，根据算法确定性地形成初始链接，并且可以根据存储器中的任何坏块的模式进行优化。 随着额外的坏块出现，链接被更新，通过替换与优质块链接的坏块，优选地与它们所替换的块相同的存储器子阵列来更新。

    Scheduling of housekeeping operations in flash memory systems
    6.
    发明授权
    Scheduling of housekeeping operations in flash memory systems 有权
    安排闪存系统中的内务管理操作

    公开(公告)号：US07565478B2

    公开(公告)日：2009-07-21

    申请号：US11949618

    申请日：2007-12-03

    申请人： Alan David Bennett ,  Sergey Anatolievich Gorobets ,  Andrew Tomlin ,  Charles Schroter

    发明人： Alan David Bennett ,  Sergey Anatolievich Gorobets ,  Andrew Tomlin ,  Charles Schroter

    IPC分类号： G06F12/02 ,  G06F13/00

    CPC分类号： G11C16/349 ,  G06F12/0246 ,  G06F2212/7205

    摘要： A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated to perform memory system housekeeping operations in the foreground during execution of a host command, wherein the housekeeping operations are unrelated to execution of the host command. Both one or more such housekeeping operations and execution of the host command are performed within a time budget established for executing that particular command. One such command is to write data being received to the memory. One such housekeeping operation is to level out the wear of the individual blocks that accumulates through repetitive erasing and re-programming.

    摘要翻译： 操作一个可重新编程的非易失性存储器系统，例如闪存EEPROM系统，其具有分组为可同时擦除的单元块的存储器单元，以在主机命令的执行期间在前台执行存储器系统管理操作，其中， 内务管理操作与主机命令的执行无关。 在为执行该特定命令建立的时间预算内执行一个或多个此类内务处理操作和主机命令的执行。 一个这样的命令是将正在接收的数据写入存储器。 一个这样的内务处理操作是通过重复擦除和重新编程来平衡累积的各个块的磨损。

    Non-volatile memory and method with multi-stream update tracking
    7.
    发明授权
    Non-volatile memory and method with multi-stream update tracking 有权
    非易失性存储器和具有多流更新跟踪的方法

    公开(公告)号：US07366826B2

    公开(公告)日：2008-04-29

    申请号：US11192220

    申请日：2005-07-27

    申请人： Sergey Anatolievich Gorobets ,  Peter John Smith ,  Alan David Bennett

    发明人： Sergey Anatolievich Gorobets ,  Peter John Smith ,  Alan David Bennett

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F2212/1032 ,  G06F2212/7203

    摘要： Update data to a non-volatile memory may be recorded in at least two interleaving streams such as either into an update block or a scratch pad block depending on a predetermined condition. The scratch pad block is used to buffered update data that are ultimately destined for the update block. Synchronization information about the order recording of updates among the streams is saved with at least one of the streams. This will allow the most recently written version of data that may exist on multiple memory blocks to be identified. In one embodiment, the synchronization information is saved in a first block and is a write pointer that points to the next recording location in a second block. In another embodiment, the synchronization information is a time stamp.

    摘要翻译： 根据预定条件，将数据更新到非易失性存储器可以记录在至少两个交织流中，诸如更新块或便笺块块中。 缓冲块块用于缓冲最终发往更新块的更新数据。 与流中的更新的顺序记录的同步信息与至少一个流一起被保存。 这将允许识别可能存在于多个内存块上的最新版本的数据。 在一个实施例中，同步信息被保存在第一块中，并且是指向第二块中的下一个记录位置的写指针。 在另一个实施例中，同步信息是时间戳。

    Method for non-volatile memory with worst-case control data management
    8.
    发明申请
    Method for non-volatile memory with worst-case control data management 审中-公开
    用于具有最坏情况控制数据管理的非易失性存储器的方法

    公开(公告)号：US20080091901A1

    公开(公告)日：2008-04-17

    申请号：US11549035

    申请日：2006-10-12

    申请人： Alan David Bennett ,  Neil David Hutchison ,  Sergey Anatolievich Gorobets

    发明人： Alan David Bennett ,  Neil David Hutchison ,  Sergey Anatolievich Gorobets

    IPC分类号： G06F13/00 ,  G06F12/00

    CPC分类号： G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7205

    摘要： In a nonvolatile memory with a block management system, data written to blocks include host write data and also system control data for managing the blocks. When a block is full or no longer accepting data, it is closed after valid versions of the data on it are relocated to another block in a rewrite operation. An improved pre-emptive rewrite scheme prevents a worst-case situation where multiple rewrites to occur at once when they happened to be full at the same time. Particularly, the scheduling of the pre-emptive rewrites for control data is based on a number of considerations including the time required for each control block rewrite and the time available for control block rewrites based on the configuration of the update blocks for storing host data, the time required in the foreground host operation and the host write latency.

    摘要翻译： 在具有块管理系统的非易失性存储器中，写入块的数据包括主机写入数据以及用于管理块的系统控制数据。 当块已满或不再接受数据时，在重写操作中将其上的数据的有效版本重定位到另一个块之后，它将被关闭。 改进的优先重写方案可以防止在同时发生多次重写时立即发生多次重写的最坏情况。 特别地，用于控制数据的优先重写的调度基于多个考虑因素，包括基于用于存储主机数据的更新块的配置，每个控制块重写所需的时间和可用于控制块重写的时间， 前台主机操作所需的时间和主机写入延迟。

    Mapping address table maintenance in a memory device
    10.
    发明授权
    Mapping address table maintenance in a memory device 有权
    映射存储设备中的地址表维护

    公开(公告)号：US08250333B2

    公开(公告)日：2012-08-21

    申请号：US12348782

    申请日：2009-01-05

    申请人： Sergey Anatolievich Gorobets ,  Alexander Paley ,  Eugene Zilberman ,  Alan David Bennett ,  Shai Traister

    发明人： Sergey Anatolievich Gorobets ,  Alexander Paley ,  Eugene Zilberman ,  Alan David Bennett ,  Shai Traister

    IPC分类号： G06F12/12

    CPC分类号： G06F12/0246 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/7201 ,  G06F2212/7205

    摘要： A method and system maintains an address table for mapping logical groups to physical addresses in a memory device. The method includes receiving a request to set an entry in the address table and selecting and flushing entries in an address table cache depending on the existence of the entry in the cache and whether the cache meets a flushing threshold criteria. The flushed entries include less than the maximum capacity of the address table cache. The flushing threshold criteria includes whether the address table cache is full or if a page exceeds a threshold of changed entries. The address table and/or the address table cache may be stored in a non-volatile memory and/or a random access memory. Improved performance may result using this method and system due to the reduced number of write operations and time needed to partially flush the address table cache to the address table.

    摘要翻译： 方法和系统维护用于将逻辑组映射到存储器设备中的物理地址的地址表。 该方法包括接收在地址表中设置条目的请求，并根据高速缓存中的条目的存在以及高速缓存是否满足冲洗阈值标准来选择和刷新地址表高速缓存中的条目。 刷新的条目包括小于地址表缓存的最大容量。 刷新阈值标准包括地址表缓存是否满或页面是否超过已更改条目的阈值。 地址表和/或地址表缓存可以存储在非易失性存储器和/或随机存取存储器中。 由于将地址表缓存部分刷新到地址表所需的写入操作次数和时间减少，因此可能会导致使用此方法和系统的性能提高。