公开(公告)号：US07576570B1

公开(公告)日：2009-08-18

申请号：US11508607

申请日：2006-08-22

申请人： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H03K5/153

CPC分类号： H03K5/153 ,  H03K5/24

摘要： Precision amplitude detection circuitry without pattern dependencies is provided that includes rectifier circuitry to output a rectified voltage signal and delay circuitry to send one or more delayed or phase-shifted versions of a differential signal input to the rectifier circuitry. The delayed versions of the differential signal input may be delayed in order to reduce or eliminate the dips in the input seen by the rectifier. This may help correct for low rectified voltage levels. The signal amplitude detection circuitry of the present invention may be incorporated on the input pin of any programmable logic resource and may be included in communication circuitry of a PLD. The precision amplitude detection circuitry may operate in the Gbps (gigabit per second) range.

摘要翻译： 提供了没有图形相关性的精密幅度检测电路，其包括整流电路，用于输出整流电压信号和延迟电路，以将一个或多个差分信号输入的延迟或相移版本发送到整流器电路。 可以延迟差分信号输入的延迟版本，以便减少或消除由整流器看到的输入中的下降。 这可能有助于校正低整流电压电平。 本发明的信号幅度检测电路可以结合在任何可编程逻辑资源的输入引脚上，并且可以被包括在PLD的通信电路中。 精度幅度检测电路可以以Gbps（千兆位/秒）范围工作。

公开(公告)号：US07920621B2

公开(公告)日：2011-04-05

申请号：US11522284

申请日：2006-09-14

申请人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

发明人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

IPC分类号： H03H7/30

CPC分类号： H04L25/03885

摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

公开(公告)号：US08208523B2

公开(公告)日：2012-06-26

申请号：US13079420

申请日：2011-04-04

申请人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

发明人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

IPC分类号： H03H7/30

CPC分类号： H04L25/03885

摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

公开(公告)号：US20110188564A1

公开(公告)日：2011-08-04

申请号：US13079420

申请日：2011-04-04

申请人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

发明人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

IPC分类号： H03K5/125 ,  H03K5/19

CPC分类号： H04L25/03885

摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

公开(公告)号：US07586983B1

公开(公告)日：2009-09-08

申请号：US11510446

申请日：2006-08-24

申请人： Sergey Shumarayev ,  Wilson Wong ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Sergey Shumarayev ,  Wilson Wong ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H03K5/159 ,  H04B1/10

CPC分类号： H04L25/03057

摘要： In high speed receiver circuitry (e.g., on a programmable logic device (PLD) or the like), decision feedback equalization (DFE) circuitry is used to at least partly cancel unwanted offset (e.g., from other elements of the receiver). The data input to the receiver is tristated; and then each DFE tap coefficient is varied in turn to find coefficient values that are associated with transitions between oscillation and non-oscillation of the receiver output signal. The coefficient values found in this way are used to select trial values. If the output signal of the receiver does not oscillate when these trial values are used, the process is repeated starting from these (or subsequent) trial values until a final set of trial values does allow oscillation of the receiver output signal.

摘要翻译： 在高速接收机电路（例如，在可编程逻辑器件（PLD）等上）中，使用判决反馈均衡（DFE）电路来至少部分地消除不期望的偏移（例如，从接收机的其他元件）。 输入到接收机的数据被三态化; 然后依次改变每个DFE抽头系数，以找到与接收机输出信号的振荡和非振荡之间的转换相关联的系数值。 以这种方式找到的系数值用于选择试验值。 如果接收机的输出信号在使用这些试验值时不振荡，则从这些（或后续）试验值开始重复该过程，直到最终的试验值确定允许接收器输出信号的振荡。

公开(公告)号：US20080069276A1

公开(公告)日：2008-03-20

申请号：US11522284

申请日：2006-09-14

申请人： Wilson Wong ,  Doris Po Ching Chan ,  Simardeep Maangat ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

发明人： Wilson Wong ,  Doris Po Ching Chan ,  Simardeep Maangat ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

IPC分类号： H04B1/10

CPC分类号： H04L25/03885

摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

公开(公告)号：US07782935B1

公开(公告)日：2010-08-24

申请号：US11514490

申请日：2006-08-31

申请人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Tin H. Lai

发明人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Tin H. Lai

IPC分类号： H03H7/30

CPC分类号： H03H11/26 ,  H04L25/03878 ,  H04L2025/0349

摘要： Methods and circuits are presented for providing equalization, including decision feedback equalization (DFE), to high data-rate signals. Half-rate delay-chain circuitry produces delayed samples of an input signal using two or more delay-chain circuits operating at a fraction of the input signal data-rate. Two delay-chain circuits operating at one-half the input signal data-rate may be used. More generally, n delay-chain circuits operating at 1/n the input signal data-rate may be used. Multiplexer circuitry combines the outputs of the delay-chain circuits to produce an output signal including samples of the input signal at the input signal data-rate. Duplicate path DFE circuitry includes two paths used to provide DFE equalization while reducing the load of the DFE circuitry on the circuitry that precedes it. A first path produces delayed samples of a DFE signal, while a second path produces the DFE output signal from the delayed samples.

摘要翻译： 提出了用于向高数据速率信号提供均衡的方法和电路，包括判决反馈均衡（DFE）。 半速率延迟链电路使用以输入信号数据速率的一小部分工作的两个或多个延迟链电路产生输入信号的延迟采样。 可以使用以输入信号数据速率的一半工作的两个延迟链电路。 更一般地，可以使用以1 / n输入信号数据速率工作的n个延迟链电路。 多路复用器电路组合延迟链电路的输出以产生包括输入信号数据速率的输入信号样本的输出信号。 重复路径DFE电路包括用于提供DFE均衡的两个路径，同时减少DFE电路之前的电路上的DFE电路的负载。 第一路径产生DFE信号的延迟采样，而第二路径产生来自延迟采样的DFE输出信号。

公开(公告)号：US08120429B1

公开(公告)日：2012-02-21

申请号：US12787722

申请日：2010-05-26

申请人： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

发明人： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

IPC分类号： H03L7/00 ,  H03K3/03

CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K3/35613 ,  H03K2005/00228 ,  H03K2005/00234

摘要： Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.

摘要翻译： 提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。 本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。 一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。 电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。 该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。

公开(公告)号：US07777526B2

公开(公告)日：2010-08-17

申请号：US12134777

申请日：2008-06-06

申请人： Sergey Shumarayev ,  Thungoc M. Tran ,  Wilson Wong ,  Simardeep Maangat

发明人： Sergey Shumarayev ,  Thungoc M. Tran ,  Wilson Wong ,  Simardeep Maangat

IPC分类号： H03K19/094

CPC分类号： H03K19/018514 ,  H03F3/45197 ,  H03F2203/45494 ,  H03F2203/45686

摘要： Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuit elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade.

摘要翻译： 集成电路中晶体管变化/失配引起的信号偏移变化可能会降低。 在一个实施例中，缓冲电路具有可变值电路元件。 进行偏移变化测量，并校准可变值电路元件以减少测量的偏移变化。 在另一个实施例中，多级缓冲器的每个放大级提供可变增益。 级联的总直流增益不均匀地分布在整个级中，在级联开始时比放大器级提供更多的直流增益。 在级联开始时也可以提供一个额外的前级放大器级。

公开(公告)号：US07728674B1

公开(公告)日：2010-06-01

申请号：US11437558

申请日：2006-05-19

申请人： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

发明人： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

IPC分类号： H03L7/00

CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K3/35613 ,  H03K2005/00228 ,  H03K2005/00234

摘要： Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.

摘要翻译： 提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。 本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。 一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。 电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。 该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。