公开(公告)号：US20180033639A1

公开(公告)日：2018-02-01

申请号：US15444597

申请日：2017-02-28

申请人： Seung Jae JUNG ,  Sang Joon YOON ,  Yong Hyun KWON ,  Dae Hyun JANG ,  Ha Na KIM

发明人： Seung Jae JUNG ,  Sang Joon YOON ,  Yong Hyun KWON ,  Dae Hyun JANG ,  Ha Na KIM

IPC分类号： H01L21/311 ,  H01L21/308 ,  H01L21/3065 ,  H01L27/115 ,  H01L29/10

CPC分类号： H01L21/31144 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/31116 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1037

摘要： A method of manufacturing a semiconductor device includes alternately stacking mold insulating layers and sacrificial layers on a substrate; forming channel holes penetrating through the mold insulating layers and the sacrificial layers and allowing recessed regions to be formed in the substrate; cleaning a surface of the recessed regions in such a manner that processes of forming a first protective layer in an upper region of the channel holes and performing an anisotropic dry etching process on the recessed regions in a lower portion of the channel holes are alternately repeated one or more times, in-situ; and forming epitaxial layers on the recessed regions of the substrate.

公开(公告)号：US20150137205A1

公开(公告)日：2015-05-21

申请号：US14467571

申请日：2014-08-25

申请人： Ki Jeong KIM ,  Jung Ik OH ,  Sung Soo AHN ,  Dae Hyun JANG

发明人： Ki Jeong KIM ,  Jung Ik OH ,  Sung Soo AHN ,  Dae Hyun JANG

IPC分类号： H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L29/7889 ,  H01L27/11517 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

摘要： According to example embodiments, a memory device includes a substrate, a channel region on the substrate, a plurality of gate electrode layers stacked on each other on the substrate, and a plurality of contact plugs. The gate electrode layers are adjacent to the channel region and extend in one direction to define a pad region. The gate electrode layers include first and second gate electrode layers. The contact plugs are connected to the gate electrode layers in the pad region. At least one of the contact plugs is electrically insulated from the from the first gate electrode layer and electrically connected to the second gate electrode layer by penetrating through the first gate electrode layer.

摘要翻译： 根据示例性实施例，存储器件包括衬底，衬底上的沟道区，在衬底上彼此堆叠的多个栅电极层和多个接触插塞。 栅极电极层与沟道区域相邻并且在一个方向上延伸以限定衬垫区域。 栅极电极层包括第一和第二栅电极层。 接触插塞连接到焊盘区域中的栅极电极层。 所述接触插塞中的至少一个与所述第一栅极电极层电绝缘，并且通过穿过所述第一栅极电极层而与所述第二栅电极层电连接。