公开(公告)号：US20080291737A1

公开(公告)日：2008-11-27

申请号：US12119060

申请日：2008-05-12

申请人： Seunghyun MOON ,  Kihwan CHOI ,  Jaesung SIM ,  Jungdal CHOI

发明人： Seunghyun MOON ,  Kihwan CHOI ,  Jaesung SIM ,  Jungdal CHOI

IPC分类号： G11C16/06

CPC分类号： G11C16/3404

摘要： Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device.

摘要翻译： 编程或擦除具有电荷存储层的非易失性存储器件的方法包括执行至少一个单元编程或擦除循环，每个单元编程或擦除循环包括应用编程脉冲，擦除脉冲，时间延迟，软擦除脉冲， 软编程脉冲和/或验证脉冲作为对非易失性存储器件的一部分（例如，字线或衬底）的正或负电压。

公开(公告)号：US20130285006A1

公开(公告)日：2013-10-31

申请号：US13742598

申请日：2013-01-16

申请人： Jintaek PARK ,  Youngwoo PARK ,  Jungdal CHOI

发明人： Jintaek PARK ,  Youngwoo PARK ,  Jungdal CHOI

IPC分类号： H01L45/00

CPC分类号： H01L45/1206 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1683

摘要： A variable resistance memory device includes a selection transistor, which includes a first doped region and a second doped region, a vertical electrode coupled to the first doped region of the selection transistor, a bit line coupled to the second doped region of the selection transistor, a plurality of word lines stacked on the substrate along a sidewall of the vertical electrode, variable resistance patterns between the word lines and the vertical electrode, and an insulating isolation layer between the word lines. The variable resistance patterns are spaced apart from each other in a direction normal to a top surface of the substrate by the insulating isolation layer.

摘要翻译： 可变电阻存储器件包括选择晶体管，其包括第一掺杂区和第二掺杂区，耦合到选择晶体管的第一掺杂区的垂直电极，耦合到选择晶体管的第二掺杂区的位线， 沿着垂直电极的侧壁堆叠在基板上的多个字线，字线和垂直电极之间的可变电阻图案以及字线之间的绝缘隔离层。 可变电阻图案通过绝缘隔离层在垂直于衬底的顶表面的方向上彼此间隔开。

公开(公告)号：US20130134377A1

公开(公告)日：2013-05-30

申请号：US13606789

申请日：2012-09-07

申请人： Jintaek PARK ,  Youngwoo PARK ,  Jungdal CHOI

发明人： Jintaek PARK ,  Youngwoo PARK ,  Jungdal CHOI

IPC分类号： H01L27/26 ,  H01L27/22

CPC分类号： H01L27/249 ,  H01L27/228 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

摘要： Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other.

摘要翻译： 提供半导体存储器件。 该装置可以包括彼此连接以构成选择线组的第一和第二选择线，顺序地堆叠在第一和第二选择线中的每一个上的多个字线，在第一和第二选择线之间排列成一行的垂直电极 选择线，在选择线组的两侧中的每一侧排列成行的多个位线插头以及与字线交叉并将位线插头彼此连接的位线。

公开(公告)号：US20110073930A1

公开(公告)日：2011-03-31

申请号：US12884668

申请日：2010-09-17

申请人： Yong-Lack CHOI ,  Sunghoi HUR ,  Jaeduk LEE ,  Jungdal CHOI

发明人： Yong-Lack CHOI ,  Sunghoi HUR ,  Jaeduk LEE ,  Jungdal CHOI

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42336

摘要： Semiconductor devices and methods of forming the same. The semiconductor devices include a tunnel insulation layer on a substrate, a floating gate on the tunnel insulation layer, a gate insulation layer on the floating gate, a low-dielectric constant (low-k) region between the top of the floating gate and the gate insulation layer, the low-k region having a lower dielectric constant than a silicon oxide, and a control gate on the gate insulation layer.

摘要翻译： 半导体器件及其形成方法。 半导体器件包括在衬底上的隧道绝缘层，隧道绝缘层上的浮动栅极，浮置栅极上的栅极绝缘层，浮动栅极的顶部和第二栅极之间的低介电常数（低k）区域 栅极绝缘层，具有比氧化硅更低的介电常数的低k区域以及栅极绝缘层上的控制栅极。

公开(公告)号：US20130093005A1

公开(公告)日：2013-04-18

申请号：US13652998

申请日：2012-10-16

申请人： Jang-Gn YUN ,  Kwang Soo SEOL ,  Jungdal CHOI

发明人： Jang-Gn YUN ,  Kwang Soo SEOL ,  Jungdal CHOI

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L27/1157 ,  H01L27/11582

摘要： Three-dimensional (3D) semiconductor memory devices are provided. According to the 3D semiconductor memory device, a gate structure includes gate patterns and insulating patterns alternately stacked on a semiconductor substrate. A vertical active pattern penetrates the gate structure. A gate dielectric layer is disposed between a sidewall of the vertical active pattern and each of the gate patterns. A semiconductor pattern is disposed on the gate structure and is connected to the vertical active pattern. A string drain region is formed in a portion of the semiconductor pattern and is spaced apart from the vertical active pattern.

摘要翻译： 提供三维（3D）半导体存储器件。 根据3D半导体存储器件，栅极结构包括交替层叠在半导体衬底上的栅极图案和绝缘图案。 垂直有源图案穿过栅极结构。 栅介质层设置在垂直有源图案的侧壁和每个栅极图案之间。 半导体图案设置在栅极结构上并连接到垂直有源图案。 串联漏极区域形成在半导体图案的一部分中并且与垂直有源图案间隔开。