公开(公告)号：US09224493B2

公开(公告)日：2015-12-29

申请号：US14280920

申请日：2014-05-19

申请人： Changhyun Lee ,  Jungdal Choi ,  Byeong-In Choe

发明人： Changhyun Lee ,  Jungdal Choi ,  Byeong-In Choe

IPC分类号： G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C8/10 ,  G11C11/56 ,  G11C16/04 ,  G11C29/00

CPC分类号： G11C16/26 ,  G11C8/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3436 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/00

摘要： A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.

摘要翻译： 非易失性存储器件通过补偿闪存单元的阈值电压而提高了可靠性。 非易失性存储器件包括：存储单元阵列和电压发生器，用于在执行读取操作时将选择读取电压提供给选择字线，并将未选择读取电压提供给未选择的字线;以及将验证电压提供给选择字线 以及当执行编程操作时，对未选字线的取消选择读取电压。 电压发生器在执行编程操作时将第一未读选择电压提供给与选择字线相邻的上字线和下字线之间的至少一个，并且将第二未选择读电压提供给上 当执行读操作时，字线和与选择字线相邻的下字线。

公开(公告)号：US20150084114A1

公开(公告)日：2015-03-26

申请号：US14554859

申请日：2014-11-26

申请人： Juhyung KIM ,  Changseok Kang ,  Sung-II Chang ,  Jungdal Choi

发明人： Juhyung KIM ,  Changseok Kang ,  Sung-II Chang ,  Jungdal Choi

IPC分类号： H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11529 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42348 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7883

摘要： A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.

摘要翻译： 非易失性存储器件可以包括半导体衬底和半导体衬底上的隔离层，其中隔离层限定半导体衬底的有源区。 可以在半导体衬底的有源区上设置隧道绝缘层，并且可以在隧道绝缘层上设置电荷存储图案。 可以在电荷存储图案上提供界面层图案，并且可以在界面层图案上提供阻挡绝缘图案。 此外，块绝缘图案可以包括高k介电材料，并且界面层图案和阻挡绝缘图案可以包括不同的材料。 可以在阻挡绝缘层上设置控制栅电极，使得阻挡绝缘图案位于界面层图案和控制栅电极之间。 还讨论了相关方法。

公开(公告)号：US08295097B2

公开(公告)日：2012-10-23

申请号：US12795196

申请日：2010-06-07

申请人： ByungKyu Cho ,  Kwang Soo Seol ,  Sunghoi Hur ,  Jungdal Choi

发明人： ByungKyu Cho ,  Kwang Soo Seol ,  Sunghoi Hur ,  Jungdal Choi

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/32 ,  G11C16/0483 ,  G11C16/3418

摘要： A channel pre-charge method of a nonvolatile memory device including a cell string includes pre-charging a channel of the cell string according to a first word line bias condition and pre-charging the channel of the cell string according to a second word line bias condition, different than the first word line bias condition.

摘要翻译： 包括单元串的非易失性存储器件的通道预充电方法包括根据第一字线偏置条件对单元串的通道进行预充电，并根据第二字线偏置对单元串的通道进行预充电 条件，不同于第一个字线偏差条件。

公开(公告)号：US20120052674A1

公开(公告)日：2012-03-01

申请号：US13214462

申请日：2011-08-22

申请人： Jaegoo LEE ,  Youngwoo Park ,  Jungdal Choi

发明人： Jaegoo LEE ,  Youngwoo Park ,  Jungdal Choi

IPC分类号： H01L21/8239

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/7827 ,  H01L29/7926

摘要： A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate. The method also includes forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate, patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate, removing one of the first and second sacrificial layers to form recessed regions in the mold stack, forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates, forming gates in the recessed regions, forming air gaps between the gates by removing the other of the first and second sacrificial layers, and forming an insulation layer pattern in the word line cuts.

摘要翻译： 一种制造半导体存储器件的方法包括在衬底上形成模具堆叠，并且模具叠层包括交替层叠在衬底上的第一牺牲层和第二牺牲层。 该方法还包括形成多个垂直通道，其穿过模具叠层并与衬底接触，图案化模具叠层以形成垂直通道之间的字线切口，字线切割暴露衬底，去除第一和第二 牺牲层，以在模具堆叠中形成凹陷区域，形成数据存储层，数据存储层的至少一部分形成在垂直沟道和栅极之间，在凹陷区域中形成栅极，在栅极之间形成气隙，通过 去除第一和第二牺牲层中的另一个，并且在字线切割中形成绝缘层图案。

公开(公告)号：US08064259B2

公开(公告)日：2011-11-22

申请号：US12617972

申请日：2009-11-13

申请人： Changhyun Lee ,  Jungdal Choi ,  Yoocheol Shin ,  Yongsik Yim

发明人： Changhyun Lee ,  Jungdal Choi ,  Yoocheol Shin ,  Yongsik Yim

IPC分类号： G11C11/34

CPC分类号： G11C16/0466

摘要： A nonvolatile memory device includes a word line group including a plurality of middle word lines and an edge word line having charge storage patterns on a substrate. A peripheral line is disposed on one side of the word line group so that the edge word line is between the peripheral word line and the middle word lines. The peripheral line includes an insulating layer and a gate electrode. Charge storage patterns of the middle and edge word lines are separated from each other, and a charge storage pattern of the edge word line extends on one side to be connected to the insulating layer of the peripheral line. Methods of forming nonvolatile memory devices are also disclosed.

摘要翻译： 非易失性存储器件包括一个包括多个中间字线的字线组和在衬底上具有电荷存储图案的边缘字线。 外围线设置在字线组的一侧，使得边缘字线在周边字线和中间字线之间。 外围线包括绝缘层和栅电极。 中间和边缘字线的电荷存储模式彼此分离，并且边缘字线的电荷存储模式在一侧延伸以连接到外围线的绝缘层。 还公开了形成非易失性存储器件的方法。

公开(公告)号：US08059466B2

公开(公告)日：2011-11-15

申请号：US12656083

申请日：2010-01-15

申请人： Changhyun Lee ,  Jungdal Choi ,  Byeong-In Choe

发明人： Changhyun Lee ,  Jungdal Choi ,  Byeong-In Choe

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5642

摘要： Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell configured to provide interference for the selected memory cell and programming the selected memory cell depending on the adjusted program-verify-voltage.

摘要翻译： 提供了一种非易失性存储器系统及其编程方法。 非易失性存储器系统的编程方法包括：参考要写入被配置为为所选存储器单元提供干扰的干扰单元的程序数据来调整所选存储器单元的编程验证电压，并根据 调整后的程序验证电压。

公开(公告)号：US20110103154A1

公开(公告)日：2011-05-05

申请号：US12917634

申请日：2010-11-02

申请人： ByungKyu Cho ,  Kwang Soo Seol ,  Sunghoi Hur ,  Jungdal Choi

发明人： ByungKyu Cho ,  Kwang Soo Seol ,  Sunghoi Hur ,  Jungdal Choi

IPC分类号： G11C16/12 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C16/3418

摘要： Provided is a local self-boosting method of a flash memory device including at least one string having memory cells respectively connected to wordlines. The local self-boosting method includes forming a potential well at a channel of the string and forming potential walls at the potential well to be disposed at both sides of a channel of a selected one of the memory cells. The channel of the selected memory cell is locally limited by the potential walls and boosted when a program voltage is applied to the selected memory cell.

摘要翻译： 提供了一种闪存器件的局部自增强方法，其包括至少一个具有分别连接到字线的存储单元的串。 局部自增强方法包括在串的通道处形成势阱，并在势阱处形成位于所选存储单元的通道两侧的电势壁。 所选择的存储单元的通道在局部受到潜在的壁限制，并且当将程序电压施加到所选择的存储单元时升压。

公开(公告)号：US09379244B2

公开(公告)日：2016-06-28

申请号：US14668490

申请日：2015-03-25

申请人： Sung Gi Hur ,  TaeYong Kwon ,  Sangsu Kim ,  Jungdal Choi

发明人： Sung Gi Hur ,  TaeYong Kwon ,  Sangsu Kim ,  Jungdal Choi

IPC分类号： H01L29/04 ,  H01L29/66 ,  H01L23/31 ,  H01L27/12 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/088

CPC分类号： H01L29/66553 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7849

摘要： A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.

公开(公告)号：US08873294B2

公开(公告)日：2014-10-28

申请号：US13295335

申请日：2011-11-14

申请人： Sunil Shim ,  Jaehoon Jang ,  Jungdal Choi ,  Woonkyung Lee ,  Kihyun Kim

发明人： Sunil Shim ,  Jaehoon Jang ,  Jungdal Choi ,  Woonkyung Lee ,  Kihyun Kim

IPC分类号： G11C16/16 ,  G11C16/14 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  H01L29/792 ,  G11C16/30 ,  H01L27/115

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/30 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided are erase methods for a memory device which includes a substrate and multiple cell strings provided on the substrate, each cell string including multiple cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the cell strings; applying a ground voltage to string selection lines connected with selection transistors of the cell strings; applying a word line erase voltage to word lines connected with memory cells of the cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage.

摘要翻译： 提供了一种存储器件的擦除方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个单元晶体管。 所述擦除方法包括将地电压施加到与所述电池串的地选择晶体管连接的接地选择线; 将接地电压施加到与电池串的选择晶体管连接的串选择线; 对与单元串的存储单元连接的字线施加字线擦除电压; 向基板施加擦除电压; 响应于施加所述擦除电压来控制所述接地选择线的电压; 以及响应于施加所述擦除电压来控制所述串选择线的电压。

公开(公告)号：US20140145137A1

公开(公告)日：2014-05-29

申请号：US14090803

申请日：2013-11-26

申请人： Hyunsu Ju ,  Eunmi Kim ,  Yoocheol Shin ,  Min Kyu Yang ,  Jungdal Choi

发明人： Hyunsu Ju ,  Eunmi Kim ,  Yoocheol Shin ,  Min Kyu Yang ,  Jungdal Choi

IPC分类号： H01L45/00

CPC分类号： H01L45/08 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/146

摘要： Resistive memory devices are provided having a gate stack including insulating layers and gates stacked on a substrate in a vertical direction, a channel penetrating the gate stack in the vertical direction to be electrically connected to the substrate, a gate insulating layer provided between the channel and the gates, and a variable resistance layer disposed along an extending direction of the channel. The gate stack may include an alcove formed by recessing the gate in a horizontal direction. The variable resistance layer may extend toward the alcove in the horizontal direction and be overlapped with at least one of the gates in the horizontal direction. Related methods are also provided.

摘要翻译： 提供电阻式存储器件，其具有包括垂直方向上堆叠在基板上的绝缘层和栅极的栅极堆叠，在垂直方向上穿过栅极堆叠的沟道以电连接到衬底;栅极绝缘层，设置在沟道和 栅极和沿通道的延伸方向设置的可变电阻层。 栅极堆叠可以包括通过在水平方向上使栅极凹陷而形成的凹室。 可变电阻层可以在水平方向上朝向凹室延伸，并且在水平方向上与至少一个栅极重叠。 还提供了相关方法。