公开(公告)号：US07706114B2

公开(公告)日：2010-04-27

申请号：US11867003

申请日：2007-10-04

申请人： Shao-Chang Huang ,  Chiun-Chi Shen ,  Hsin-Ming Chen

发明人： Shao-Chang Huang ,  Chiun-Chi Shen ,  Hsin-Ming Chen

IPC分类号： H02H9/00

CPC分类号： H02H9/046

摘要： When an electrostatic discharge event occurs to a connection pad of a chip, an electrostatic discharge detector layout in a feedback loop is able to detect an induced electrostatic discharge voltage for generating a control signal. A pass transistor can be turned off by the control signal for isolating the induced electrostatic discharge voltage, and the internal circuit of the chip can be protected from being damaged by the induced electrostatic discharge voltage. Furthermore, the designed circuit based on electrostatic discharge isolation technique for protecting the internal circuit of the chip is compatible with programmable circuits, and the connection pad can be furnished with burning signals or logic signals.

摘要翻译： 当芯片的连接焊盘发生静电放电事件时，反馈回路中的静电放电检测器布局能够检测用于产生控制信号的感应静电放电电压。 可以通过用于隔离感应静电放电电压的控制信号关闭传输晶体管，并且可以防止芯片的内部电路被感应的静电放电电压损坏。 此外，基于用于保护芯片内部电路的静电放电隔离技术的设计电路与可编程电路兼容，并且连接焊盘可以配备燃烧信号或逻辑信号。

公开(公告)号：US20090091870A1

公开(公告)日：2009-04-09

申请号：US11867003

申请日：2007-10-04

申请人： Shao-Chang Huang ,  Chiun-Chi Shen ,  Hsin-Ming Chen

发明人： Shao-Chang Huang ,  Chiun-Chi Shen ,  Hsin-Ming Chen

IPC分类号： H02H9/04 ,  H02H1/00

CPC分类号： H02H9/046

摘要： When an electrostatic discharge event occurs to a connection pad of a chip, an electrostatic discharge detector layout in a feedback loop is able to detect an induced electrostatic discharge voltage for generating a control signal. A pass transistor can be turned off by the control signal for isolating the induced electrostatic discharge voltage, and the internal circuit of the chip can be protected from being damaged by the induced electrostatic discharge voltage. Furthermore, the designed circuit based on electrostatic discharge isolation technique for protecting the internal circuit of the chip is compatible with programmable circuits, and the connection pad can be furnished with burning signals or logic signals.

摘要翻译： 当芯片的连接焊盘发生静电放电事件时，反馈回路中的静电放电检测器布局能够检测用于产生控制信号的感应静电放电电压。 可以通过用于隔离感应静电放电电压的控制信号关闭传输晶体管，并且可以防止芯片的内部电路被感应的静电放电电压损坏。 此外，基于用于保护芯片内部电路的静电放电隔离技术的设计电路与可编程电路兼容，并且连接焊盘可以配备燃烧信号或逻辑信号。

公开(公告)号：US07660087B2

公开(公告)日：2010-02-09

申请号：US12106346

申请日：2008-04-21

申请人： Shao-Chang Huang ,  Hsin-Ming Chen

发明人： Shao-Chang Huang ,  Hsin-Ming Chen

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： An ESD avoiding circuit includes a first ESD protection unit, an ESD detection unit, a switch unit, and an RC filter unit. The first ESD protection unit transmits an ESD current between a first conducting path and a second conducting path. The ESD detection unit is coupled to the first conducting path. The ESD detection unit includes an input terminal, and an output terminal coupled to the first ESD protection unit for detecting an ESD and controlling the first ESD protection unit to conduct the ESD current according to a detection result. The switch unit is coupled between the first conducting path and a core circuit and conducts the first conducting path to the core circuit according to signals of the input terminal and the output terminal of the ESD detection unit. The RC filter unit couples a first voltage to the input terminal of the ESD detection unit.

摘要翻译： ESD避免电路包括第一ESD保护单元，ESD检测单元，开关单元和RC滤波器单元。 第一ESD保护单元在第一导电路径和第二导电路径之间传输ESD电流。 ESD检测单元耦合到第一导电路径。 ESD检测单元包括输入端子和耦合到第一ESD保护单元的输出端子，用于检测ESD，并根据检测结果控制第一ESD保护单元导通ESD电流。 开关单元耦合在第一导电路径和核心电路之间，并且根据ESD检测单元的输入端子和输出端子的信号将第一导电路径导通到核心电路。 RC滤波器单元将第一电压耦合到ESD检测单元的输入端。

公开(公告)号：US20090168280A1

公开(公告)日：2009-07-02

申请号：US12106346

申请日：2008-04-21

申请人： Shao-Chang Huang ,  Hsin-Ming Chen

发明人： Shao-Chang Huang ,  Hsin-Ming Chen

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： An ESD avoiding circuit includes a first ESD protection unit, an ESD detection unit, a switch unit, and an RC filter unit. The first ESD protection unit transmits an ESD current between a first conducting path and a second conducting path. The ESD detection unit is coupled to the first conducting path. The ESD detection unit includes an input terminal, and an output terminal coupled to the first ESD protection unit for detecting an ESD and controlling the first ESD protection unit to conduct the ESD current according to a detection result. The switch unit is coupled between the first conducting path and a core circuit and conducts the first conducting path to the core circuit according to signals of the input terminal and the output terminal of the ESD detection unit. The RC filter unit couples a first voltage to the input terminal of the ESD detection unit.

摘要翻译： ESD避免电路包括第一ESD保护单元，ESD检测单元，开关单元和RC滤波器单元。 第一ESD保护单元在第一导电路径和第二导电路径之间传输ESD电流。 ESD检测单元耦合到第一导电路径。 ESD检测单元包括输入端子和耦合到第一ESD保护单元的输出端子，用于检测ESD，并根据检测结果控制第一ESD保护单元导通ESD电流。 开关单元耦合在第一导电路径和核心电路之间，并且根据ESD检测单元的输入端子和输出端子的信号将第一导电路径导通到核心电路。 RC滤波器单元将第一电压耦合到ESD检测单元的输入端。

公开(公告)号：US20080316660A1

公开(公告)日：2008-12-25

申请号：US11765857

申请日：2007-06-20

申请人： Shao-Chang Huang ,  Ke-Hong Chen ,  Hsin-Ming Chen

发明人： Shao-Chang Huang ,  Ke-Hong Chen ,  Hsin-Ming Chen

IPC分类号： H02H9/04 ,  H02H9/00

CPC分类号： H02H9/046 ,  H02H3/05

摘要： An electrostatic discharge (ESD) avoiding circuit comprises an ESD detecting unit and a switch unit. The ESD detecting unit is coupled to a first conductive path for detecting whether the ESD happened or not. The switch unit is coupled between the first conductive path and a core circuit for switching whether the first conductive path is conducted to the core circuit or not according to a detection result of the ESD detecting unit. The ESD avoiding circuit can avoid an electrostatic current transmitting to the core circuit when the ESD is happened, and the ESD avoiding circuit can make the normal signal/voltage providing to the core circuit for operating when the ESD isn't happened.

摘要翻译： 静电放电（ESD）避免电路包括ESD检测单元和开关单元。 ESD检测单元耦合到第一导电路径，用于检测ESD是否发生。 开关单元耦合在第一导电路径和核心电路之间，用于根据ESD检测单元的检测结果切换第一导电路径是否传导到核心电路。 当ESD发生时，ESD避免电路可以避免静电电流传输到核心电路，并且ESD避免电路可以使得在ESD不发生时提供给核心电路的正常信号/电压进行工作。

公开(公告)号：US20100006924A1

公开(公告)日：2010-01-14

申请号：US12171301

申请日：2008-07-11

申请人： Hsin-Ming Chen ,  Shao-Chang Huang ,  Shih-Chen Wang ,  Tsung-Mu Lai ,  Ming-Chou Ho ,  Chrong-Jung Lin

发明人： Hsin-Ming Chen ,  Shao-Chang Huang ,  Shih-Chen Wang ,  Tsung-Mu Lai ,  Ming-Chou Ho ,  Chrong-Jung Lin

IPC分类号： H01L27/112

CPC分类号： H01L27/112 ,  H01L27/11206 ,  H01L27/11521

摘要： A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a third doped region, a first dielectric layer, a select gate, a second dielectric layer, a first channel, a second channel and a silicide layer is provided. The first doped region, the second doped region and the third doped region are disposed apart in a substrate. The first dielectric layer is disposed on the substrate between the first doped region and the second doped region. The select gate is disposed on the first dielectric layer. The second dielectric layer is disposed on the substrate between the second doped region and the third doped region. The silicide layer is disposed on the first doped region, the second doped region and the third doped region. The OTP-ROM stores data by a punch-through effect occurring between the second doped region and the third doped region.

摘要翻译： 一种包括衬底，第一掺杂区域，第二掺杂区域，第三掺杂区域，第一介电层，选择栅极，第二介电层，第一沟道 ，提供第二通道和硅化物层。 第一掺杂区域，第二掺杂区域和第三掺杂区域设置在衬底中。 第一介电层设置在第一掺杂区和第二掺杂区之间的衬底上。 选择栅极设置在第一电介质层上。 第二介电层设置在第二掺杂区和第三掺杂区之间的衬底上。 硅化物层设置在第一掺杂区域，第二掺杂区域和第三掺杂区域上。 OTP-ROM通过发生在第二掺杂区域和第三掺杂区域之间的穿透效应来存储数据。

公开(公告)号：US20090283814A1

公开(公告)日：2009-11-19

申请号：US12122739

申请日：2008-05-19

申请人： Hsin-Ming Chen ,  Shao-Chang Huang ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Chrong-Jung Lin

发明人： Hsin-Ming Chen ,  Shao-Chang Huang ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Chrong-Jung Lin

IPC分类号： H01L27/112

CPC分类号： H01L27/112 ,  G11C17/16 ,  H01L23/5256 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： A non-volatile memory cell includes an ion well of a semiconductor substrate; a first half-transistor having a firs select gate, a first diffusion region in the ion well, and a first gate dielectric layer between the first select gate and the ion well; a second half-transistor disposed adjacent to the first half-transistor, wherein the second half-transistor has a second select gate spaced apart from the first select gate, a second diffusion region in the ion well, and a second gate dielectric layer between the second select gate and the ion well. The first and second half-transistors are mirror-symmetrical to each other.

摘要翻译： 非易失性存储单元包括半导体衬底的离子阱; 具有第一选择栅极的第一半晶体管，离子阱中的第一扩散区域和第一选择栅极与离子阱之间的第一栅极介电层; 与所述第一半晶体管相邻设置的第二半晶体管，其中所述第二半晶体管具有与所述第一选择栅极间隔开的第二选择栅极，所述离子阱中的第二扩散区域和所述第二栅极介电层之间的第二栅极介电层 第二选择门和离子阱。 第一和第二半晶体管彼此镜像对称。

公开(公告)号：US08787092B2

公开(公告)日：2014-07-22

申请号：US13418352

申请日：2012-03-13

申请人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Hsin-Ming Chen

发明人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Hsin-Ming Chen

IPC分类号： G11C16/04 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0433

摘要： The invention provides a nonvolatile memory apparatus. The nonvolatile memory apparatus comprises a plurality of memory cells and a signal generator. The memory cells are arranged in an array, and each of the memory cells has a control gate terminal, a floating gate, a source line terminal, a bit-line terminal, a selected gate terminal and a word-line terminal. The signal generator is coupled to the memory cells. When the nonvolatile memory apparatus executes a programming operation, the signal generator provides a programming signal to the control gate terminals of a plurality of inhibited memory cells among the memory cells. Wherein, the programming signal is a pulse signal with a direct-current (DC) offset voltage.

摘要翻译： 本发明提供一种非易失性存储装置。 非易失性存储装置包括多个存储单元和信号发生器。 存储单元被布置成阵列，并且每个存储单元具有控制栅极端子，浮动栅极，源极线端子，位线端子，所选择的栅极端子和字线端子。 信号发生器耦合到存储单元。 当非易失性存储器件执行编程操作时，信号发生器向存储器单元中的多个禁止的存储单元的控制栅极端提供编程信号。 其中编程信号是具有直流（DC）偏移电压的脉冲信号。

公开(公告)号：US20130234228A1

公开(公告)日：2013-09-12

申请号：US13572731

申请日：2012-08-13

申请人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ren Chen

发明人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ren Chen

IPC分类号： H01L27/115

CPC分类号： H01L27/11558 ,  G11C16/0433 ,  G11C2216/10 ,  H01L29/42328 ,  H01L29/7883 ,  H01L29/7885

摘要： An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.

摘要翻译： 可擦除可编程单一多晶硅非易失性存储器包括具有浮置栅极的浮栅晶体管，浮置栅极下方的栅极氧化物层和沟道区域; 和擦除栅极区，其中浮置栅极延伸到擦除栅极区并且与擦除栅极区相邻。 栅极氧化物层包括位于浮动栅极晶体管的沟道区上方的第一部分和擦除栅极区上方的第二部分，并且栅极氧化物层的第一部分的厚度与第二部分的厚度不同 栅氧化层。

公开(公告)号：US20130234227A1

公开(公告)日：2013-09-12

申请号：US13415185

申请日：2012-03-08

申请人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Shih-Chen Wang ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Shih-Chen Wang ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： H01L27/115

CPC分类号： H01L29/42328 ,  G11C16/0408 ,  H01L27/11558 ,  H01L29/7885

摘要： An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.

摘要翻译： 可擦除可编程单一多晶硅非易失性存储器包括包括选择栅极，第一p型掺杂区域和第二p型掺杂区域的第一PMOS晶体管，其中选择栅极连接到选择栅极电压，并且第一 p型掺杂区域连接到源极线电压; 包括第二p型掺杂区的第二PMOS晶体管，第三p型掺杂区和浮置栅，其中第三p型掺杂区连接到位线电压; 以及与浮置栅极相邻的擦除栅极区域，其中擦除栅极区域连接到擦除线电压。