公开(公告)号：US20190131459A1

公开(公告)日：2019-05-02

申请号：US16091225

申请日：2017-04-07

Applicant: Sharp Kabushiki Kaisha

Inventor： Tadayoshi MIYAMOTO ,  Akihiro ODA

IPC: H01L29/786

Abstract: A gate driver TFT 30 includes: a gate electrode 30a; a channel portion 30d overlapping the gate electrode 30a with a gate insulating film 16 disposed therebetween and constructed from an oxide semiconductor film 17 that is a semiconductor film; a source electrode 30b connected to one end of the channel portion 30d; a drain electrode 30c connected to another end of the channel portion 30d; and an intermediate electrode 22 connected to the channel portion 30d at a position at which a distance L1 to the drain electrode 30c is greater than a distance L2 to the source electrode 30b.

公开(公告)号：US20160190181A1

公开(公告)日：2016-06-30

申请号：US14650681

申请日：2013-12-02

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Naoki UEDA ,  Akihiro ODA ,  Hirohiko NISHIKI ,  Tohru OKABE

IPC: H01L27/12 ,  H01L29/786 ,  G09G3/36 ,  H01L29/45 ,  H01L29/417 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L27/1248 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0286 ,  G11C19/287 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

Abstract: A semiconductor device includes: a plurality of thin film transistors including a gate electrode, a gate dielectric layer, a semiconductor layer formed on the gate dielectric layer, and a source electrode and a drain electrode provided on the semiconductor layer; a source metal layer including a global line which supplies a common signal to the plurality of thin film transistors, the global line being made of the same electrically conductive film as the source electrode and drain electrode; and a dielectric protection layer covering the plurality of thin film transistors and the source metal layer. The source metal layer includes a lower layer and an upper layer stacked on a portion of the lower layer. The global line has a first layer structure including the lower layer and the upper layer, and at least a portion of each source electrode and of each drain electrode that is located on the semiconductor layer has a second layer structure including the lower layer but not including the upper layer.

Abstract translation: 半导体器件包括：多个薄膜晶体管，包括栅极电极，栅极电介质层，形成在栅极电介质层上的半导体层，以及设置在半导体层上的源电极和漏电极; 源极金属层，包括向多个薄膜晶体管提供公共信号的全局线，全局线由与源电极和漏电极相同的导电膜制成; 以及覆盖多个薄膜晶体管和源极金属层的介电保护层。 源极金属层包括层叠在下层的一部分上的下层和上层。 全局线具有包括下层和上层的第一层结构，并且位于半导体层上的每个源电极和每个漏电极的至少一部分具有包括下层但不包括的第二层结构 上层。

公开(公告)号：US20200243568A1

公开(公告)日：2020-07-30

申请号：US16491229

申请日：2018-03-02

Applicant: Sharp Kabushiki Kaisha

Inventor： Akihiro ODA ,  Yujiro TAKEDA ,  Shogo MURASHIGE ,  Hiroshi MATSUKIZONO

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/417 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02

Abstract: An active matrix substrate includes: a substrate (1); a peripheral circuit including a plurality of first TFTs (10); and a plurality of second TFTs (20), wherein each of the first and second TFTs (10, 20) includes: a gate electrode (3A, 3B); a gate insulating layer (5); an oxide semiconductor layer (7A, 7B) including a channel region (7Ac, 7Bc), a source contact region (7As, 7Bs) and a drain contact region (7Ad, 7Bd), wherein the source contact region and the drain contact region are located on opposite sides of the channel region; a source electrode (8A, 8B) that is in contact with the source contact region and a drain electrode (9A, 9B) that is in contact with the drain contact region; the oxide semiconductor layer of the first TFTs and the second TFTs is formed from the same oxide semiconductor film; a carrier concentration in the channel regions (7Ac) of the first TETs is higher than a carrier concentration in the channel regions (7Bc) of the second TETs.

公开(公告)号：US20160063955A1

公开(公告)日：2016-03-03

申请号：US14783548

申请日：2014-02-25

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Kaoru YAMAMOTO ,  Yasuyuki OGAWA ,  Akihiro ODA ,  Masahiro TOMIDA

IPC: G09G5/10

CPC classification number: G09G5/10 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/022 ,  G09G2330/027 ,  H03K3/356026

Abstract: A display device includes: a display unit, a driver unit, and a control unit. The display unit includes a plurality of pixel units arranged in a matrix. The driver unit includes an output transistor configured to drive a plurality of scanning lines connected to the plurality of pixel units. The control unit is configured to supply to the driver unit in a display period, a signal for displaying an image on the display unit, and control a bias state of the output transistor in a display suspension period, so that an absolute value of a threshold voltage of the output transistor which is increased in the display period decreases.

Abstract translation: 显示装置包括：显示单元，驱动单元和控制单元。 显示单元包括以矩阵形式布置的多个像素单元。 驱动器单元包括输出晶体管，其被配置为驱动连接到多个像素单元的多条扫描线。 控制单元被配置为在显示周期中向驱动器单元供应用于在显示单元上显示图像的信号，并且在显示暂停时段中控制输出晶体管的偏置状态，使得阈值的绝对值 在显示周期中增加的输出晶体管的电压降低。

公开(公告)号：US20200152802A1

公开(公告)日：2020-05-14

申请号：US16619532

申请日：2018-06-04

Applicant: Sharp Kabushiki Kaisha

Inventor： Yujiro TAKEDA ,  Hiroshi MATSUKIZONO ,  Akihiro ODA ,  Shogo MURASHIGE ,  Kohhei TANAKA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/24 ,  H01L29/66

Abstract: An active matrix substrate of an embodiment of the present invention includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate. Each oxide semiconductor TFT includes a lower gate electrode provided on the substrate, a gate insulating layer covering the lower gate electrode, an oxide semiconductor layer provided on the gate insulating layer, a source electrode which is in contact with the source contact region of the oxide semiconductor layer, a drain electrode which is in contact with the drain contact region of the oxide semiconductor layer, an insulating layer covering the oxide semiconductor layer, the source electrode and the drain electrode, and an upper gate electrode provided on the insulating layer. When viewed in a normal direction of the substrate, the upper gate electrode does not overlap a first electrode which is one of the source electrode and the drain electrode, and a second electrode which is the other of the source electrode and the drain electrode does not overlap the lower gate electrode.

公开(公告)号：US20190079330A1

公开(公告)日：2019-03-14

申请号：US16123045

申请日：2018-09-06

Applicant: Sharp Kabushiki Kaisha

Inventor： Kaoru YAMAMOTO ,  Akihiro ODA ,  Tadayoshi MIYAMOTO

IPC: G02F1/1345 ,  G02F1/1343 ,  G02F1/1333 ,  G09G3/36 ,  H01L27/12

Abstract: An active matrix substrate includes a demultiplexer circuit which includes a plurality of DMX circuit TFTs. Each of the DMX circuit TFTs includes a front-gate electrode (FG) supplied with a control signal from one of a plurality of control signal main lines ASW, BSW and a back-gate electrode (BG) supplied with a back-gate signal which is different from the control signal. The plurality of DMX circuit TFTs includes first DMX circuit TFTs (T1a, T1b) and second DMX circuit TFTs (T2a, T2b). The back-gate electrode of each of the first DMX circuit TFTs (T1a, T1b)is connected with a first back-gate signal main line (BGL(1)) which supplies a first back-gate signal and, the back-gate electrode of each of the second DMX circuit TFTs (T2a, T2b)is connected with a second back-gate signal main line (BGL(2)) which supplies a second back-gate signal which is different from the first back-gate signal.

公开(公告)号：US20180356660A1

公开(公告)日：2018-12-13

申请号：US15781253

申请日：2016-12-02

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiro TOMIDA ,  Akihiro ODA

IPC: G02F1/1368 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/768

CPC classification number: G02F1/1368 ,  G09F9/30 ,  H01L21/28 ,  H01L21/76829 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/41 ,  H01L29/417 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/786 ,  H01L29/78696

Abstract: A plurality of TFTs provided in a peripheral circuit region of an active matrix substrate of an embodiment includes a TFT (10A) in which, when viewed in a direction perpendicular to a substrate (11A), the length in the channel width direction of an oxide semiconductor layer (14A), WAos, is smaller than the length in the channel width direction of a gate electrode (12A), WAg, the length in the channel width direction of a source electrode region (15AR) in which the source electrode (15A) is in contact with the oxide semiconductor layer (14A), WAs, is smaller than the length in the channel width direction of the oxide semiconductor layer (14A), WAos, and the drain electrode (16A) is in contact with the oxide semiconductor layer (14A) in a plurality of drain electrode regions (16AR) arranged in the channel width direction, and the overall length in the channel width direction of the plurality of drain electrode regions (16AR), WAd, is smaller than the length in the channel width direction of the oxide semiconductor layer (14A), WAos.

公开(公告)号：US20170200827A1

公开(公告)日：2017-07-13

申请号：US15315395

申请日：2015-05-28

Applicant: Sharp Kabushiki Kaisha

Inventor： Akihiro ODA

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/66 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78621

Abstract: A semiconductor device (100) includes a thin film transistor (5) provided on a substrate and including a gate electrode (12), a gate insulating layer (20) in contact with the gate electrode, an oxide semiconductor layer (18) located so as to partially overlap the gate electrode with the gate insulating layer being located between the oxide semiconductor layer and the gate electrode, a source electrode (14), and a drain electrode (16). The oxide semiconductor layer (18) includes a gate facing region (18g) overlapping the gate electrode as seen in a direction of normal to the substrate; and offset regions (18os, 18od) provided adjacent to the gate facing region, the offset regions not overlapping the gate electrode, the source electrode or the drain electrode as seen in the direction of normal to the substrate. The gate facing region has a carrier concentration in the range of 1×1017/cm3 or greater and 1×1019/cm3 or less.

公开(公告)号：US20160042806A1

公开(公告)日：2016-02-11

申请号：US14774558

申请日：2014-02-12

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Yasuyuki OGAWA ,  Kaoru YAMAMOTO ,  Akihiro ODA ,  Masahiro TOMIDA

IPC: G11C19/28 ,  G09G3/36

CPC classification number: G11C19/28 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/043

Abstract: A shift register circuit has a plurality of unit circuits that are cascade-connected to one another and that output received pulse signals as output signals in accordance with a clock signal, the shift register circuit sequentially outputting the output signals from the plurality of respective unit circuits. The output circuits each include a double-gate transistor having first gate electrode that controls conductivity between the drain electrode and the source electrode, and a second gate electrode formed through an insulating layer and disposed to face the first gate electrode across a semiconductor layer between the drain electrode and the source electrode. The shift register circuit applies a prescribed voltage to the second gate electrode in accordance with a voltage applied to the first gate electrode.

Abstract translation: 移位寄存器电路具有彼此级联的多个单位电路，并且根据时钟信号输出接收到的脉冲信号作为输出信号，移位寄存器电路顺次地输出来自多个单元电路的输出信号 。 输出电路各自包括双栅极晶体管，其具有控制漏电极和源电极之间的导电性的第一栅电极，以及通过绝缘层形成的第二栅电极，并且设置成跨越第一栅电极跨越半导体层 漏电极和源电极。 移位寄存器电路根据施加到第一栅电极的电压向第二栅电极施加规定的电压。