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    Alloy barrier layers for semiconductors
    2.
    发明授权
    Alloy barrier layers for semiconductors 有权
    半导体合金阻挡层

    公开(公告)号：US06362526B1

    公开(公告)日：2002-03-26

    申请号：US09169277

    申请日：1998-10-08

    申请人： Shekhar Pramanick ,  John A. Iacoponi

    发明人： Shekhar Pramanick ,  John A. Iacoponi

    IPC分类号： H01L2348

    CPC分类号： H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S257/915 ,  H01L2924/00

    摘要： A semiconductor barrier layer and manufacturing method therefor for copper interconnects which is a tantalum-titanium, tantalum-titanium nitride, tantalum-titanium sandwich. The tantalum in the tantalum-titanium alloy bonds strongly with the semiconductor dielectric, the tantalum-titanium nitride acts as the barrier to prevent diffusion of copper, and the titanium bonds strongly with the copper.

    摘要翻译： 一种用于铜互连的半导体阻挡层及其制造方法，其为钽钛，钽 - 氮化钛，钽 - 钛三明治。 钽 - 钛合金中的钽与半导体电介质牢固地结合，钽 - 氮化钛作为屏障阻止铜的扩散，钛与铜强烈结合。

    Barrier materials for metal interconnect in a semiconductor device
    3.
    发明授权
    Barrier materials for metal interconnect in a semiconductor device 有权
    用于半导体器件中的金属互连的阻挡材料

    公开(公告)号：US06344691B1

    公开(公告)日：2002-02-05

    申请号：US09664863

    申请日：2000-09-19

    申请人： John A. Iacoponi ,  Shekhar Pramanick

    发明人： John A. Iacoponi ,  Shekhar Pramanick

    IPC分类号： H01L2348

    CPC分类号： H01L21/76846 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is provided with a tantalum layer to line the channels and vias of a semiconductor, a tungsten nitride layer at a low temperature on the tantalum layer, and a copper conductor layer on the tungsten nitride layer. The tungsten nitride acts as a highly efficient copper barrier material with high resistivity while the tantalum layer acts as a conductive barrier material to reduce the overall resistance of the barrier layer.

    摘要翻译： 半导体器件设置有钽层，以在钽层上对半导体的通道和通孔，低温下的氮化钨层和氮化钨层上的铜导体层进行排列。 氮化钨作为具有高电阻率的高效铜阻挡材料，而钽层用作导电阻挡材料，以降低阻挡层的整体电阻。

    Barrier materials for metal interconnect
    4.
    发明授权
    Barrier materials for metal interconnect 有权
    金属互连的阻隔材料

    公开(公告)号：US6150268A

    公开(公告)日：2000-11-21

    申请号：US186781

    申请日：1998-11-04

    申请人： John A. Iacoponi ,  Shekhar Pramanick

    发明人： John A. Iacoponi ,  Shekhar Pramanick

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

    CPC分类号： H01L21/76846 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002

    摘要： A method is provided for manufacturing a semiconductor device by: depositing a tantalum layer to line the channels and vias of a semiconductor; depositing a tungsten nitride layer at a low temperature on the tantalum layer; and depositing a copper conductor layer on the tungsten nitride layer. The tungsten nitride acts as a highly efficient copper barrier material with high resistivity while the tantalum layer acts as a conductive barrier material to reduce the overall resistance of the barrier layer.

    摘要翻译： 提供一种用于制造半导体器件的方法，即：沉积钽层以对半导体的沟道和通孔进行排列; 在钽层上沉积低温氮化钨层; 以及在所述氮化钨层上沉积铜导体层。 氮化钨作为具有高电阻率的高效铜阻挡材料，而钽层用作导电阻挡材料以降低阻挡层的整体电阻。

    Method of manufacturing a transistor with local insulator structure
    7.
    发明授权
    Method of manufacturing a transistor with local insulator structure 有权
    制造具有局部绝缘体结构的晶体管的方法

    公开(公告)号：US06380019B1

    公开(公告)日：2002-04-30

    申请号：US09187498

    申请日：1998-11-06

    申请人： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

    发明人： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

    IPC分类号： H01L2976

    CPC分类号： H01L21/74 ,  H01L29/0649 ,  H01L29/6659

    摘要： A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

    摘要翻译： 薄膜完全耗尽的绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）利用局部绝缘结构。 局部绝缘结构包括沟道区下方的埋置二氧化硅区域。 MOSFET体的厚度非常小，而在沟道区域和掩埋的二氧化硅区域之外可用的硅可用于源极和漏极区域中足够的硅化物深度。 掩埋的二氧化硅区域可以通过沟槽隔离技术或LOCOS技术形成。

    Chemical-mechanical polishing of semiconductors
    8.
    发明授权
    Chemical-mechanical polishing of semiconductors 有权
    半导体化学机械抛光

    公开(公告)号：US06350678B1

    公开(公告)日：2002-02-26

    申请号：US09534906

    申请日：2000-03-23

    申请人： Shekhar Pramanick ,  Kai Yang

    发明人： Shekhar Pramanick ,  Kai Yang

    IPC分类号： H01L214763

    CPC分类号： H01L21/3212 ,  H01L21/7684

    摘要： A method for manufacturing an integrated circuit using damascene processes is provided in which planar surfaces of contacting conductive metal channels and vias are subjected to chemical-mechanical polishing under a pressure which avoids cold working and to two steps of chemical-mechanical polishing in which the first step is performed using a slurry with a first sized abrasive to expose a first dielectric layer in which the conductive metal channel is embedded and to provide a planar polished surface of the conductive material, and a second step is performed using a second slurry with a second sized abrasive larger than said first sized abrasive to provide a planar rough-polished surface of the conductive material. The second polishing also performed at a pressure which avoids cold working, which causes a highly polycrystalline structure and a high dislocation density, in the conductive material at its planar polished surface.

    摘要翻译： 提供一种使用镶嵌工艺制造集成电路的方法，其中接触导电金属通道和通孔的平坦表面在避免冷加工的压力下进行化学机械抛光，并进行两步化学机械抛光，其中第一 使用具有第一尺寸磨料的浆料进行步骤以暴露其中嵌入有导电金属通道的第一介电层，并提供导电材料的平面抛光表面，并且使用第二浆料进行第二步骤 大于所述第一尺寸磨料的磨料，以提供导电材料的平面粗糙抛光表面。 第二次抛光也在避免冷加工的压力下进行，这导致在其平面抛光表面的导电材料中导致高度多晶结构和高位错密度。

    Self-aligned silicide gate technology for advanced deep submicron MOS device
    9.
    发明授权
    Self-aligned silicide gate technology for advanced deep submicron MOS device 有权
    用于先进深亚微米MOS器件的自对准硅化物栅极技术

    公开(公告)号：US06239452B1

    公开(公告)日：2001-05-29

    申请号：US09320682

    申请日：1999-05-27

    申请人： Qi Xiang ,  Shekhar Pramanick ,  Ming-Ren Lin

    发明人： Qi Xiang ,  Shekhar Pramanick ,  Ming-Ren Lin

    IPC分类号： H01L2184

    CPC分类号： H01L29/6659 ,  H01L21/28097 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/665

    摘要： A deep submicron MOS device having a self-aligned silicide gate structure and a method for forming the same is provided so as to overcome the problems of poly-Si depletion and boron penetration. A first Nickel silicide layer is formed between a gate oxide and a polycrystalline silicon gate electrode. Further, second Nickel silicide layers are formed over highly-doped source/drain regions. In this fashion, the reliability of the MOS device will be enhanced.

    摘要翻译： 提供了具有自对准硅化物栅极结构的深亚微米MOS器件及其形成方法，以克服多Si耗尽和硼渗透的问题。 在栅极氧化物和多晶硅栅电极之间形成第一镍硅化物层。 此外，第二镍硅化物层形成在高掺杂源/漏区上。 以这种方式，MOS器件的可靠性将得到提高。