公开(公告)号：US06511925B1

公开(公告)日：2003-01-28

申请号：US10033164

申请日：2001-10-19

申请人： Sheldon Aronowitz ,  Vladimir Zubkov ,  Helmut Puchner

发明人： Sheldon Aronowitz ,  Vladimir Zubkov ,  Helmut Puchner

IPC分类号： H01L218238

CPC分类号： H01L21/28185 ,  H01L21/2236 ,  H01L21/265 ,  H01L29/517

摘要： In accordance with the invention a high-k gate dielectric is formed by the steps of first forming a silicon oxide layer over a silicon substrate and then exposing the silicon oxide to a flux of low energy plasma containing metal ions which, when inserted into silicon oxide, form a high-k dielectric material suitable for use as a high-k gate dielectric. In one embodiment, the silicon oxide is exposed to a first plasma containing a first species of metal ions and then to a plasma of another species of metal ions which, when inserted into the silicon oxide with the metal ions in the first plasma, further increase the dielectric constant of the silicon oxide.

摘要翻译： 根据本发明，通过以下步骤形成高k栅极电介质：首先在硅衬底上形成氧化硅层，然后将氧化硅暴露于含有金属离子的低能量等离子体的焊剂中，该金属离子当插入到氧化硅 形成适合用作高k栅极电介质的高k电介质材料。 在一个实施例中，氧化硅暴露于含有第一种金属离子的第一等离子体，然后暴露于另一种金属离子的等离子体，当等离子体中的金属离子插入到氧化硅中时，其进一步增加 氧化硅的介电常数。

公开(公告)号：US06831348B2

公开(公告)日：2004-12-14

申请号：US10383031

申请日：2003-03-06

申请人： Helmut Puchner ,  Sheldon Aronowitz

发明人： Helmut Puchner ,  Sheldon Aronowitz

IPC分类号： H01L2900

CPC分类号： H01L21/7621

摘要： A method of forming a narrow isolation structure in a semiconducting substrate. The isolation structure is a trench that has a bottom and sidewalls, and that is to be filled with an isolating material. The isolating material has desired electrical properties and desired chemical properties, and is substantially reactively grown from the semiconducting substrate. A precursor material layer is formed on the bottom of the trench and on the sidewalls of the trench. The precursor material layer has electrical properties and chemical properties that are substantially similar to the desired electrical properties and the desired chemical properties of the isolating material. A substantial portion of the precursor material layer is removed from the bottom of the trench to expose the semiconducting substrate at the bottom of the trench, while leaving a substantial portion of the precursor material layer on the sidewalls of the trench. The isolating material is reactively grown in the trench, where the isolating material preferentially grows from the exposed semiconducting substrate at the bottom of the trench at a first rate. The precursor material layer at least partially inhibits formation of the isolating material from the semiconducting substrate at the sidewalls of the trench. The isolating material forms from the sidewalls of the trench at a second rate, where the first rate is substantially higher than the second rate. Thus, by forming a precursor layer that inhibits formation of the isolation material at the sidewalls of the trench, the isolation material preferentially grows from the bottom of the trench rather than expanding sideways from the sidewalls of the trench, which tends to widen the isolation structure. Because the precursor layer has properties that are substantially similar to those that are desired in the isolation material, the precursor layer remains at the sidewalls of the trench near the edge of the isolation structure. Therefore, the isolation structure functions as desired, but is narrower than it otherwise would be, if the precursor layer had not been formed.

公开(公告)号：US06413881B1

公开(公告)日：2002-07-02

申请号：US09521312

申请日：2000-03-09

申请人： Sheldon Aronowitz ,  John Haywood ,  James P. Kimball ,  Helmut Puchner ,  Ravindra Manohar Kapre ,  Nicholas Eib

发明人： Sheldon Aronowitz ,  John Haywood ,  James P. Kimball ,  Helmut Puchner ,  Ravindra Manohar Kapre ,  Nicholas Eib

IPC分类号： H01L2131

CPC分类号： H01L21/28176 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/2822 ,  H01L21/3144 ,  H01L29/518

摘要： A process for inhibiting the passage of dopant from a gate electrode into a thin gate oxide comprises nitridation of the upper surface of the thin gate oxide, prior to formation of the gate electrode over the gate oxide, to thereby form a barrier of nitrogen atoms in the upper surface region of the gate oxide adjacent the interface between the gate oxide and the gate electrode to inhibit passage of dopant atoms from the gate electrode into the thin gate oxide during annealing of the structure. In one embodiment, a selective portion of silicon oxide on a silicon substrate may be etched to thin the oxide to the desired thickness using a nitrogen plasma with a bias applied to the silicon substrate. Nitridation of the surface of the etched silicon oxide is then carried out in the same apparatus by removing the bias from the silicon substrate.

摘要翻译： 抑制掺杂剂从栅电极通入薄栅氧化物的方法包括在栅极氧化物上形成栅电极之前，对薄栅极氧化物的上表面进行氮化，从而形成氮原子的势垒 栅极氧化物的上表面区域与栅极氧化物和栅电极之间的界面相邻，以在结构退火期间抑制掺杂剂原子从栅电极到薄栅氧化层的通过。 在一个实施例中，可以蚀刻硅衬底上的氧化硅的选择性部分，以使用施加到硅衬底的偏压的氮等离子体将氧化物稀释至期望的厚度。 然后通过从硅衬底去除偏压，在相同的装置中进行蚀刻的氧化硅的表面的氮化。

公开(公告)号：US6156620A

公开(公告)日：2000-12-05

申请号：US121283

申请日：1998-07-22

申请人： Helmut Puchner ,  Shih-Fen Huang ,  Sheldon Aronowitz

发明人： Helmut Puchner ,  Shih-Fen Huang ,  Sheldon Aronowitz

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： An isolation trench in a silicon semiconductor substrate is provided with a barrier region containing nitrogen atoms formed in the trench, contiguous with the silicon semiconductor substrate surfaces of the trench. The novel isolation trench structure of the invention is formed by forming an isolation trench in a silicon semiconductor substrate; forming in the isolation trench a barrier region by treating the trench structure with nitrogen atoms from a nitrogen plasma; and then forming a silicon oxide layer over the barrier region in the trench to confine the nitrogen atoms in the barrier region. In a preferred embodiment, a silicon oxide liner is first formed over the silicon semiconductor substrate surfaces of the trench, and then the trench structure is treated with nitrogen atoms from a nitrogen plasma to form, on the silicon semiconductor substrate surfaces of the trench, a barrier layer which contains silicon atoms, oxygen atoms, and nitrogen atoms.

摘要翻译： 在硅半导体衬底中的隔离沟槽设置有阻挡区域，该阻挡区域包含在沟槽中形成的与沟槽的硅半导体衬底表面相邻的氮原子。 本发明的新型隔离沟槽结构通过在硅半导体衬底中形成隔离沟槽而形成; 通过用氮等离子体的氮原子处理沟槽结构，在隔离沟槽中形成阻挡区; 然后在沟槽中的阻挡区域上形成氧化硅层以将氮原子限制在阻挡区域中。 在优选实施例中，首先在沟槽的硅半导体衬底表面上形成氧化硅衬垫，然后用氮等离子体的氮原子处理沟槽结构，以在沟槽的硅半导体衬底表面上形成 含有硅原子，氧原子和氮原子的阻挡层。

公开(公告)号：US06759337B1

公开(公告)日：2004-07-06

申请号：US09464297

申请日：1999-12-15

申请人： Sheldon Aronowitz ,  Valeriy Sukharev ,  John Haywood ,  James P. Kimball ,  Helmut Puchner ,  Ravindra Manohar Kapre ,  Nicholas Eib

发明人： Sheldon Aronowitz ,  Valeriy Sukharev ,  John Haywood ,  James P. Kimball ,  Helmut Puchner ,  Ravindra Manohar Kapre ,  Nicholas Eib

IPC分类号： H01L21302

CPC分类号： H01L21/31105 ,  H01L21/28176

摘要： A process for etching oxide is disclosed wherein a reproducibly accurate and uniform amount of silicon oxide can be removed from a surface of an oxide previously formed over a semiconductor substrate by exposing the oxide to a nitrogen plasma in an etch chamber while applying an rf bias to a substrate support on which the substrate is supported in the etch chamber. The thickness of the oxide removed in a given period of time may be changed by changing the amount of rf bias applied to the substrate through the substrate support.

摘要翻译： 公开了一种用于蚀刻氧化物的方法，其中可以通过在蚀刻室中暴露氧化物到氮等离子体，同时将rf偏压施加到半导体衬底上，通过在半导体衬底上预先形成的氧化物的表面，可再现性地精确和均匀的量的氧化硅 衬底支撑件，衬底支撑在蚀刻室中。 在给定时间段内去除的氧化物的厚度可以通过改变通过衬底支撑件施加到衬底的rf偏置量来改变。

公开(公告)号：US6090651A

公开(公告)日：2000-07-18

申请号：US434340

申请日：1999-11-05

申请人： Helmut Puchner ,  Sheldon Aronowitz ,  Gary K. Giust

发明人： Helmut Puchner ,  Sheldon Aronowitz ,  Gary K. Giust

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  Y10S438/929

摘要： A method of forming a supersaturated layer on a semiconductor device, where an initial phase layer is deposited on the semiconductor device. The initial phase layer has a solid phase dopant saturation level and a liquid phase dopant saturation level, where the liquid phase dopant saturation level is greater than the solid phase dopant saturation level. A concentration of a dopant is impregnated within the initial phase layers, where the concentration of the dopant is greater than the solid phase dopant saturation level and no more than about the liquid phase dopant saturation level. The initial phase layer is annealed, without appreciably heating the semiconductor device, using an amount of energy that is high enough to liquefy the initial phase layer over a melt duration. This dissolves the dopant in the liquefied initial phase layer. The amount of energy is low enough to not appreciably gasify or ablate the initial phase layer. The liquefied initial phase layer is cooled to freeze the dissolved dopant in a supersaturated, electrically activated concentration, thereby forming the supersaturated layer. An initial phase layer of either polysilicon or amorphous silicon may be deposited over a CMOS device. After laser annealing the initial phase layer with a melt duration of no more than about 100 nanoseconds, it is transformed into a doped polysilicon gate electrode that can be patterned and further processed.

摘要翻译： 在半导体器件上形成过饱和层的方法，其中初始相层沉积在半导体器件上。 初始相层具有固相掺杂剂饱和水平和液相掺杂剂饱和水平，其中液相掺杂剂饱和水平大于固相掺杂剂饱和水平。 掺杂剂的浓度浸渍在初始相层中，其中掺杂剂的浓度大于固相掺杂剂饱和水平并且不大于约液相掺杂剂饱和水平。 使用一定量的足够高的能量使熔融持续时间内的初始相层液化的能量，初始相层退火，而不明显地加热半导体器件。 这溶解了液化的初始相层中的掺杂剂。 能量的量足够低，不能明显地气化或消融初始相层。 液化的初始相层被冷却以使过溶化的掺杂剂以过饱和的电活化浓度冷冻，从而形成过饱和层。 多晶硅或非晶硅的初始相层可以沉积在CMOS器件上。 在熔融持续时间不超过约100纳秒的激光退火初始相层之后，将其转变成可被图案化并进一步处理的掺杂多晶硅栅电极。

公开(公告)号：US06613651B1

公开(公告)日：2003-09-02

申请号：US09654689

申请日：2000-09-05

申请人： Helmut Puchner ,  Sheldon Aronowitz

发明人： Helmut Puchner ,  Sheldon Aronowitz

IPC分类号： H01L2176

CPC分类号： H01L21/7621

摘要： A method of forming a narrow isolation structure in a semiconducting substrate. The isolation structure is a trench that has a bottom and sidewalls, and that is to be filled with an isolating material. The isolating material has desired electrical properties and desired chemical properties, and is substantially reactively grown from the semiconducting substrate. A precursor material layer is formed on the bottom of the trench and on the sidewalls of the trench. The precursor material layer has electrical properties and chemical properties that are substantially similar to the desired electrical properties and the desired chemical properties of the isolating material. A substantial portion of the precursor material layer is removed from the bottom of the trench to expose the semiconducting substrate at the bottom of the trench, while leaving a substantial portion of the precursor material layer on the sidewalls of the trench. The isolating material is reactively grown in the trench, where the isolating material preferentially grows from the exposed semiconducting substrate at the bottom of the trench at a first rate. The precursor material layer at least partially inhibits formation of the isolating material from the semiconducting substrate at the sidewalls of the trench. The isolating material forms from the sidewalls of the trench at a second rate, where the first rate is substantially higher than the second rate. Thus, by forming a precursor layer that inhibits formation of the isolation material at the sidewalls of the trench, the isolation material preferentially grows from the bottom of the trench rather than expanding sideways from the sidewalls of the trench, which tends to widen the isolation structure. Because the precursor layer has properties that are substantially similar to those that are desired in the isolation material, the precursor layer remains at the sidewalls of the trench near the edge of the isolation structure. Therefore, the isolation structure functions as desired, but is narrower than it otherwise would be, if the precursor layer had not been formed.

公开(公告)号：US06331468B1

公开(公告)日：2001-12-18

申请号：US09076399

申请日：1998-05-11

申请人： Sheldon Aronowitz ,  Helmut Puchner ,  Ravindra A. Kapre ,  James P. Kimball

发明人： Sheldon Aronowitz ,  Helmut Puchner ,  Ravindra A. Kapre ,  James P. Kimball

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/2652 ,  H01L21/28202 ,  H01L21/28247 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659

摘要： A process is described for using a silicon layer as an implant and out-diffusion layer, for forming defect-free source/drain regions in a semiconductor substrate, and also for subsequent formation of silicon nitride spacers. A nitrogen-containing dopant barrier layer is first formed over a single crystal semiconductor substrate by nitridating either a previously formed gate oxide layer, or a silicon layer formed over the gate oxide layer, to form a barrier layer comprising either a silicon, oxygen, and nitrogen compound or a compound of silicon and nitrogen. The nitridating may be carried out using a nitrogen plasma followed by an anneal. A polysilicon gate electrode is then formed over this barrier layer, and the exposed portions of the barrier layer remaining are removed. An amorphous silicon layer of predetermined thickness is then formed over the substrate and polysilicon gate electrode. This amorphous layer is then implanted with a dopant capable of forming a source/drain region in the underlying silicon substrate by subsequent diffusion of the implanted dopant from the amorphous silicon layer into the substrate. The structure is then annealed to diffuse the dopant from the implanted silicon layer into the substrate to form the desired source/drain regions and into the polysilicon gate electrode to dope the polysilicon. The annealing further serves to cause the amorphous silicon layer to crystalize to polycrystalline silicon (polysilicon). In one embodiment, the polysilicon layer is then nitridized to convert it to a silicon nitride layer which is then patterned to form silicon nitride spacers on the sidewalls of the polysilicon gate electrode to electrically insulate the gate electrode from the source/drain regions. The process may be further modified to also create LDD or HDD source/drain regions in the substrate (depending on the concentration of the dopant), using multiple implants into the same silicon layer or by the sequential use of several silicon layers, each of which is used as an implantation and out-diffusion layer.

公开(公告)号：US20140006730A1

公开(公告)日：2014-01-02

申请号：US13537877

申请日：2012-06-29

申请人： Suhail Zain ,  Helmut Puchner ,  Walt Anderson ,  Karthik Navalpakam

发明人： Suhail Zain ,  Helmut Puchner ,  Walt Anderson ,  Karthik Navalpakam

IPC分类号： G06F12/00

CPC分类号： G06F13/16 ,  G06F12/00 ,  G06F13/1668 ,  G06F13/1673 ,  G06F13/1694

摘要： A device can include a controller interface having at least one controller data output configured to output read data, and at least one controller data input configured to receive write data; and a memory device interface having a write data output configured to transmit the write data on rising and falling edges of a periodic signal, and a read data input configured to receive the read data at a same transmission rate as the write data.

摘要翻译： 设备可以包括控制器接口，其具有被配置为输出读取数据的至少一个控制器数据输出，以及被配置为接收写入数据的至少一个控制器数据输入; 以及存储器件接口，其具有被配置为在周期信号的上升沿和下降沿发送写入数据的写入数据输出，以及被配置为以与写入数据相同的传输速率接收读取的数据的读取数据输入。

公开(公告)号：US20050215024A1

公开(公告)日：2005-09-29

申请号：US11069501

申请日：2005-03-01

申请人： Jeong-Yeop Nahm ,  Helmut Puchner ,  Oliver Pohland ,  Yangzhong Xu

发明人： Jeong-Yeop Nahm ,  Helmut Puchner ,  Oliver Pohland ,  Yangzhong Xu

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/1045 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： Methods for fabricating diffusion regions having steep concentration profiles within MOS devices while minimizing junction capacitance degradation are provided. In particular, methods are provided which include patterning a gate structure upon a semiconductor substrate and subsequently etching a recess in exposed portions of the substrate. In some cases, the method includes forming a first dopant region within the exposed portions prior to etching the recess. The method may additionally or alternatively include implanting a second set of dopants into portions of the semiconductor substrate bordering the recess. In either case, the method includes growing an epitaxial layer within the recess and implanting a third set of dopants into the semiconductor topography to form a second dopant region extending to a depth at least within the epitaxial layer. A resulting semiconductor topography includes a source/drain region comprising an upper portion consisting essentially of first dopants of a first conductivity type.

摘要翻译： 提供了在MOS器件内制造具有陡峭浓度分布的扩散区，同时最小化结电容劣化的方法。 特别地，提供了包括在半导体衬底上图案化栅极结构并随后蚀刻衬底的暴露部分中的凹部的方法。 在一些情况下，该方法包括在蚀刻凹槽之前在暴露部分内形成第一掺杂区域。 该方法可以附加地或替代地包括将第二组掺杂剂注入到与凹部接合的半导体衬底的部分中。 在任一情况下，该方法包括在凹槽内生长外延层并将第三组掺杂剂注入到半导体形貌中以形成延伸至至少在外延层内的深度的第二掺杂区。 得到的半导体形貌包括源/漏区，其包括基本上由第一导电类型的第一掺杂剂组成的上部。